Selectable open circuit and anti-fuse element
View Patent ↗An integrated circuit is provided with a semiconductor substrate that is doped with a set concentration of an oxidizable dopant of a type that segregates to the top surface of a silicide when the semiconductor substrate is reacted to form such a silicide. A gate dielectric is on the semiconductor substrate, and a gate is on the gate dielectric. Source/drain junctions are in the semiconductor substrate. A silicide is on the source/drain junctions and dopant is segregated to the top surface of the silicide. The dopant on the top surface of the segregated dopant is oxidized to form an insulating layer of oxidized dopant above the silicide. An interlayer dielectric is above the semiconductor substrate. Contacts and connection points are in the interlayer dielectric to the insulating layer of oxidized dopant above the silicide.
1. An integrated circuit comprising: a semiconductor substrate that is doped with a set concentration of an oxidizable dopant of a type that is segregated on top of a silicide; a gate dielectric on the semiconductor substrate; a gate on the gate dielectric; source/drain junctions in the semiconductor substrate; a silicide on the source/drain junctions; segregated dopant on the top surface of the silicide; an insulating layer of oxidized dopant on the top surface of the segregated dopant above the silicide; an interlayer dielectric above the semiconductor substrate; and contacts and connection points in the interlayer dielectric to the insulating layer of oxidized dopant above the silicide, wherein the contacts and connection points further comprise closed connection points and open connection points.
2. The integrated circuit as claimed in claim 1 further comprising:
at least a portion of the insulating layer of oxidized dopant being configured as anti-fuse programmable elements; and
an electrical closed circuit through at least one of the anti-fuse programmable elements.
3. The integrated circuit as claimed in claim 1 wherein the semiconductor substrate is a silicon substrate that is doped with a set concentration of arsenic dopant to form an n-type semiconductor region.
4. The integrated circuit as claimed in claim 1 wherein the contacts in the interlayer dielectric to the insulating oxide layer above the silicide use materials selected from a group consisting of tantalum, titanium, tungsten, copper, gold, silver, an alloy thereof, a compound thereof, and a combination thereof.
5. An integrated circuit comprising: a semiconductor substrate that is doped with a set concentration of an oxidizable dopant of a type that is segregated on top of a silicide; a gate dielectric on the semiconductor substrate; a gate on the gate dielectric; source/drain junctions in the semiconductor substrate and low and high concentration regions therein of the oxidizable dopant; a silicide on the source/drain junctions and on the gate; segregated dopant from the high concentration regions on the top surface of the silicide on the source/drain junctions; an insulating layer of oxidized dopant on the top surface of the segregated dopant above the silicide; an interlayer dielectric above the semiconductor substrate; and contacts and connection points in the interlayer dielectric to the insulating layer of oxidized dopant above the high concentration regions, and to the silicide above the low concentration regions, wherein the contacts and connection points further comprise closed connection points above the low concentration regions and open connection points above the high concentration regions.
6. The integrated circuit as claimed in claim 5 further comprising:
at least a portion of the insulating layer of oxidized dopant being configured as anti-fuse programmable elements; and
an electrical closed circuit through at least one of the anti-fuse programmable elements.
7. The integrated circuit as claimed in claim 5 wherein the semiconductor substrate is a silicon substrate that is doped with a set concentration of arsenic dopant to form an n-type semiconductor region.
8. The integrated circuit as claimed in claim 5 wherein the contacts to the insulating layer of oxidized dopant and to the silicide further comprise cores within a barrier metal formed of materials selected from a group consisting of tantalum, titanium, tungsten, copper, gold, silver, an alloy thereof, a compound thereof, and a combination thereof.