Use of scanning theme implanters and annealers for selective implantation and annealing
View Patent ↗A method and system for integrated circuit (IC) processing combines an ion implantation tool and a laser anneal tool in a single unit with a shared precision X-Y scanner. A semiconductor wafer is loaded onto a the X-Y table of the scanner. Data defining the desired ion implantation is used to first customize circuit areas on the semiconductor wafer by gating ON and OFF the ion beam while semiconductor wafer is scanned. Any inadvertent ion beam interruptions are noted by storing the locations of the interruptions. The wafer is then reprocessed to correct faults caused by the interruptions. The laser anneal tool positions the laser beam over the semiconductor wafer it is then scanned while gating the laser beam ON and OFF to custom anneal the wafer devices. Again, any inadvertent laser beam interruptions are detected and the locations of the interruptions are stored for reprocessing to correct faults.
1. A method for integrated circuit (IC) processing in a single integrated ion implantation and laser anneal tool comprising the step of:
processing a semiconductor wafer in the single tool system by first scanning the semiconductor wafer under the ion implantation tool while gating an ion beam ON and OFF to selectively modify device areas on the semiconductor wafer; and
processing the wafer in the single tool system by secondly scanning the semiconductor wafer under the laser anneal tool while gating a laser beam ON and OFF to selectively anneal device areas on the semiconductor wafer.
2. The method of claim 1 further comprising detecting and storing locations on the semiconductor wafer of either unintentional ion beam or laser beam interruption.
3. The method of claim 2 further comprising the steps of:
rescanning to the locations on the semiconductor wafer of either unintentional ion beam or laser beam interruption; and
reprocessing areas on the semiconductor wafer of unintentional beam interruption, by a selectively gating ON and OFF either the ion beam or the laser beam as applicable.
4. The method of claim 1 , wherein no photoresist layer is applied to the semiconductor wafer before a step of ion implantation or a step of laser annealing.