Patent Assignment
Reel/Frame 049709/0871
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded: 2019-07-10
Received: 2019-07-10
Pages: 19
Assignor
GLOBALFOUNDRIES INC.
Executed: 2018-11-26
Assignee
ALSEPHINA INNOVATIONS INC.
303 TERRY FOX DRIVE, SUITE 300, OTTAWA, CAX, K2K 3J1, CANADA
Covered Applications
(100)
INTEGRATED CIRCUIT HAVING IMPROVED ELECTROMIGRATION PERFORMANCE AND METHOD OF FORMING SAME
App. No. 15/485,657
→
TRANSISTOR STRUCTURES AND FABRICATION METHODS THEREOF
App. No. 15/482,086
→
WAFER HANDLER AND METHODS OF MANUFACTURE
App. No. 15/432,560
→
EXTRUSION-RESISTANT SOLDER INTERCONNECT STRUCTURES AND METHODS OF FORMING
App. No. 15/421,737
→
METHOD OF UTILIZING TRENCH SILICIDE IN A GATE CROSS-COUPLE CONSTRUCT
App. No. 15/168,336
→
METHOD OF UTILIZING TRENCH SILICIDE IN A GATE CROSS-COUPLE CONSTRUCT
App. No. 15/167,347
→
INTEGRATED CIRCUITS WITH SELF ALIGNED CONTACT STRUCTURES FOR IMPROVED WINDOWS AND FABRICATION METHODS
App. No. 15/157,786
→
COMPOUND SEMICONDUCTOR STRUCTURE
App. No. 15/149,913
→
METAL LINES HAVING ETCH-BIAS INDEPENDENT HEIGHT
App. No. 15/146,510
→
GATE-TO-BODY CONTACT TO RELEASE PLASMA INDUCED CHARGING
App. No. 15/140,618
→
2D SELF-ALIGNED VIA FIRST PROCESS FLOW
App. No. 15/134,435
→
FIELD EFFECT TRANSISTOR (FET) WITH SELF-ALIGNED DOUBLE GATES ON BULK SILICON SUBSTRATE, METHODS OF FORMING, AND RELATED DESIGN STRUCTURES
App. No. 15/092,976
→
CONSTRAINED DIE ADHESION CURE PROCESS
App. No. 15/084,893
→
GATE DIELECTRIC PROTECTION FOR TRANSISTORS
App. No. 15/080,090
→
HIGH VOLTAGE LATERAL DOUBLE-DIFFUSED METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (LDMOSFET) HAVING A DEEP FULLY DEPLETED DRAIN DRIFT REGION
App. No. 15/067,307
→
PRESSURE TRANSFER PROCESS FOR THIN FILM SOLAR CELL FABRICATION
App. No. 15/018,398
→
EPITAXIALLY GROWN SILICON GERMANIUM CHANNEL FINFET WITH SILICON UNDERLAYER
App. No. 15/016,612
→
METHOD AND APPARATUS FOR A HIGH YIELD CONTACT INTEGRATION SCHEME
App. No. 15/001,390
→
HYBRID ORIENTATION FIN FIELD EFFECT TRANSISTOR AND PLANAR FIELD EFFECT TRANSISTOR
App. No. 14/994,549
→
DIRECT INJECTION MOLDED SOLDER PROCESS FOR FORMING SOLDER BUMPS ON WAFERS
App. No. 14/986,925
→
FINFET SEMICONDUCTOR DEVICE HAVING LOCAL BURIED OXIDE
App. No. 14/974,772
→
METHODS, APPARATUS AND SYSTEM FOR REDUCTION OF POWER CONSUMPTION IN A SEMICONDUCTOR DEVICE
App. No. 14/965,639
→
SEMICONDUCTOR DEVICES WITH REPLACEMENT GATE STRUCTURES
App. No. 14/963,378
→
PHOTORESIST COLLAPSE METHOD FOR FORMING A PHYSICAL UNCLONABLE FUNCTION
App. No. 14/942,228
→
INTEGRATED CIRCUITS WITH DUAL SILICIDE CONTACTS AND METHODS FOR FABRICATING SAME
App. No. 14/924,151
→
DEVICES AND METHODS OF FORMING FINFETS WITH SELF ALIGNED FIN FORMATION
App. No. 14/812,500
→
DUAL SILICIDE INTEGRATION WITH LASER ANNEALING
App. No. 14/810,065
→
FINFET FABRICATION METHOD
App. No. 14/809,216
→
ELECTRICALLY ISOLATED SiGe FIN FORMATION BY LOCAL OXIDATION
App. No. 14/808,921
→
TRANSISTOR FORMATION USING COLD WELDING
App. No. 14/795,579
→
FABRICATION OF FIELD-EFFECT TRANSISTORS WITH ATOMIC LAYER DOPING
App. No. 14/699,859
→
ELECTRONIC FUSE WITH RESISTIVE HEATER
App. No. 14/695,113
→
Laser Doping of Crystalline Semiconductors Using a Dopant-Containing Amorphous Silicon Stack for Dopant Source and Passivation
App. No. 14/691,124
→
MAKING AN EFUSE
App. No. 14/608,807
→
TEST MACRO FOR USE WITH A MULTI-PATTERNING LITHOGRAPHY PROCESS
App. No. 14/607,161
→
CATALYTIC ETCH WITH MAGNETIC DIRECTION CONTROL
App. No. 14/521,948
→
TRANSISTOR WITH BONDED GATE DIELECTRIC
App. No. 14/020,430
→
USE OF CONTACTS TO CREATE DIFFERENTIAL STRESSES ON DEVICES
App. No. 13/851,709
→
CMOS TRANSISTORS HAVING DIFFERENTIALLY STRESSED SPACERS
App. No. 13/752,388
→
HIGH PERFORMANCE LOW POWER BULK FET DEVICE AND METHOD OF MANUFACTURE
App. No. 13/732,636
→
STRUCTURE AND METHOD TO MINIMIZE REGROWTH AND WORK FUNCTION SHIFT IN HIGH-K GATE STACKS
App. No. 13/680,470
→
RAISED SOURCE/DRAIN FIELD EFFECT TRANSISTOR
App. No. 13/655,610
→
Laser Doping of Crystalline Semiconductors Using a Dopant-Containing Amorphous Silicon Stack For Dopant Source and Passivation
App. No. 13/645,926
→
INTEGRATED CIRCUIT HAVING BACK GATING, IMPROVED ISOLATION AND REDUCED WELL RESISTANCE AND METHOD TO FABRICATE SAME
App. No. 13/623,198
→
SILICON GERMANIUM FILM FORMATION METHOD AND STRUCTURE
App. No. 13/616,994
→
METHOD FOR SELF ALIGNED METAL GATE CMOS
App. No. 13/617,528
→
ENHANCING MOSFET PERFORMANCE BY OPTIMIZING STRESS PROPERTIES
App. No. 13/613,081
→
SEMICONDUCTOR DEVICE HAVING CONTACT STRUCTURE THAT INCLUDES METAL SILICIDE LAYER AND DIFFUSION BARRIER LAYER FORMED SIMULTANEOUSLY FROM METAL ALLOY LAYER DIRECTLY DEPOSITED ON SILICON SUBSTRATE
App. No. 13/611,363
→
RAISED SOURCE/DRAIN FIELD EFFECT TRANSISTOR
App. No. 13/602,644
→
INTERCONNECT STRUCTURE FABRICATED WITHOUT DRY PLASMA ETCH PROCESSING
App. No. 13/603,017
→
STRUCTURE FOR USE IN FABRICATION OF PIN HETEROJUNCTION TFET
App. No. 13/571,392
→
SELF-ALIGNED CONTACTS
App. No. 13/568,832
→
A CHIP ASSEMBLY APPARATUS
App. No. 13/566,467
→
Metal-Semiconductor Intermixed Regions
App. No. 13/564,181
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HIGH-K DIELECTRIC GATE STRUCTURES RESISTANT TO OXIDE GROWTH AT THE DIELECTRIC/SILICON SUBSTRATE INTERFACE AND METHODS OF MANUFACTURE THEREOF
App. No. 13/556,795
→
UNIFORMLY ALIGNED WELL AND ISOLATION REGIONS IN A SUBSTRATE AND RESULTING STRUCTURE
App. No. 13/552,695
→
AIR GAP-CONTAINING INTERCONNECT STRUCTURE HAVING PHOTO-PATTERNABLE LOW K MATERIAL
App. No. 13/540,931
→
DOPANT MARKER FOR PRECISE RECESS CONTROL
App. No. 13/471,756
→
Device component forming method with a trim step prior to sidewall image transfer (SIT) processing
App. No. 13/456,282
→
METHOD AND STRUCTURE FOR REWORKING ANTIREFLECTIVE COATING OVER SEMICONDUCTOR SUBSTRATE
App. No. 13/455,505
→
INTERCONNECT STRUCTURE HAVING A VIA WITH A VIA GOUGING FEATURE AND DIELECTRIC LINER SIDEWALLS FOR BEOL INTEGRATION
App. No. 13/448,780
→
ELECTROMIGRATION-RESISTANT LEAD-FREE SOLDER INTERCONNECT STRUCTURES
App. No. 13/427,940
→
STRAINED MOS DEVICE AND METHODS FOR ITS FABRICATION
App. No. 13/418,114
→
MULTIPLE PATTERNING USING IMPROVED PATTERNABLE LOW-K DIELECTRIC MATERIALS
App. No. 13/407,141
→
SILICON-ON-INSULATOR TRANSISTOR WITH SELF-ALIGNED BORDERLESS SOURCE/DRAIN CONTACTS
App. No. 13/345,201
→
Method and Semiconductor Device Comprising a Protection Layer for Reducing Stress Relaxation in a Dual Stress Liner Approach
App. No. 13/337,949
→
ISOLATION WITH OFFSET DEEP WELL IMPLANTS
App. No. 13/228,998
→
METHOD FOR FORMING A METAL SILICIDE HAVING A LOWER POTENTIAL FOR CONTAINING MATERIAL DEFECTS
App. No. 12/948,463
→
CMOS STRUCTURE AND METHOD OF MANUFACTURE
App. No. 12/899,127
→
METHOD OF FABRICATING HETERO-JUNCTION BIPOLAR TRANSISTOR (HBT)
App. No. 12/732,560
→
ELECTROMIGRATION RESISTANT ALUMINUM-BASED METAL INTERCONNECT STRUCTURE
App. No. 12/552,641
→
DUAL EXPOSURE TRACK ONLY PITCH SPLIT PROCESS
App. No. 12/551,801
→
BEOL INTERCONNECT STRUCTURES AND RELATED FABRICATION METHODS
App. No. 12/547,770
→
METHODS FOR FABRICATING NON-PLANAR SEMICONDUCTOR DEVICES HAVING STRESS MEMORY
App. No. 12/512,814
→
FIELD EFFECT RESISTOR FOR ESD PROTECTION
App. No. 12/490,749
→
STRUCTURE AND METHOD FOR MANUFACTURING DEVICE WITH A V-SHAPE CHANNEL NMOSFET
App. No. 12/488,783
→
IMPLANTATION USING A HARDMASK
App. No. 12/469,710
→
ETCHING OF TUNGSTEN SELECTIVE TO TITANIUM NITRIDE
App. No. 12/468,297
→
ISOLATION WITH OFFSET DEEP WELL IMPLANTS
App. No. 12/464,206
→
METHOD OF FABRICATING SEMICONDUCTOR TRANSISTOR DEVICES WITH ASYMMETRIC EXTENSION AND/OR HALO IMPLANTS
App. No. 12/463,221
→
IMPLEMENTING VERTICAL AIRGAP STRUCTURES BETWEEN CHIP METAL LAYERS
App. No. 12/430,300
→
REDUCING CONTAMINATION OF SEMICONDUCTOR SUBSTRATES DURING BEOL PROCESSING BY PERFORMING A DEPOSITION/ETCH CYCLE DURING BARRIER DEPOSITION
App. No. 12/418,857
→
METHOD FOR PROVIDING ROTATIONALLY SYMMETRIC ALIGNMENT MARKS FOR AN ALIGNMENT SYSTEM THAT REQUIRES ASYMMETRIC GEOMETRIC LAYOUT
App. No. 12/388,851
→
STRUCTURE AND METHOD FOR BACK END OF THE LINE INTEGRATION
App. No. 12/351,436
→
CENTRIFUGAL METHOD FOR FILING HIGH ASPECT RATIO BLIND MICRO VIAS WITH POWDERED MATERIALS FOR CIRCUIT FORMATION
App. No. 12/247,894
→
DAMASCENE WIRING FABRICATION METHODS INCORPORATING DIELECTRIC CAP ETCH PROCESS WITH HARD MASK RETENTION
App. No. 12/243,440
→
MOSFET WITH LATERALLY GRADED CHANNEL REGION AND METHOD FOR MANUFACTURING SAME
App. No. 12/238,041
→
ERASEABLE NONVOLATILE MEMORY WITH SIDEWALL STORAGE
App. No. 12/190,657
→
POLYCONDUCTOR LINE END FORMATION AND RELATED MASK
App. No. 12/178,072
→
DUAL WORK-FUNCTION SINGLE GATE STACK
App. No. 12/175,528
→
STRUCTURE AND METHOD FOR ENHANCED TRIPLE WELL LATCHUP ROBUSTNESS
App. No. 12/169,667
→
MASK HAVING IMPLANT STOPPING LAYER
App. No. 12/145,922
→
VERTICAL P-N JUNCTION DEVICE AND METHOD OF FORMING SAME
App. No. 12/145,857
→
MASK FORMING AND IMPLANTING METHODS USING IMPLANT STOPPING LAYER
App. No. 12/145,915
→
REDUCING WIRE EROSION DURING DAMASCENE PROCESSING
App. No. 12/142,094
→
POLYCARBOSILANE BURIED ETCH STOPS IN INTERCONNECT STRUCTURES
App. No. 12/140,854
→
STRESS ENHANCED TRANSISTOR DEVICES AND METHODS OF MAKING
App. No. 12/136,195
→
STRUCTURES AND METHODS TO ENHANCE CU INTERCONNECT ELECTROMIGRATION (EM) PERFORMANCE
App. No. 12/132,806
→
REDUCING THE CREATION OF CHARGE TRAPS AT GATE DIELECTRICS IN MOS TRANSISTORS BY PERFORMING A HYDROGEN TREATMENT
App. No. 12/125,490
→
METHOD OF FORMING AN EMBEDDED BARRIER LAYER FOR PROTECTION FROM CHEMICAL MECHANICAL POLISHING PROCESS
App. No. 12/123,799
→