Implementing vertical airgap structures between chip metal layers

1. A method for implementing vertical airgap structures between chip metal layers comprising the steps of:

forming a first metal layer;

depositing a first layer of silicon dioxide dielectric onto said first metal layer;

etching a vertical air gap from said first layer of silicon dioxide dielectric above said first metal layer; said etched vertical air gap having a set width substantially equal to a width of a metal signal trace of said first metal layer;

depositing a second layer of silicon dioxide dielectric and sealing said vertical air gap;

etching a next trace layer from said second layer of silicon dioxide dielectric and etching a via opening through said second and first layers of silicon dioxide dielectric; and

depositing a second metal layer in said etched next trace layer and depositing metal into said via opening; said etched vertical air gap having a set height substantially less than to a distance between said first metal layer and said second metal layer.

2. The method for implementing vertical airgap structures as recited in claim 1 wherein etching said vertical air gap from said first layer of silicon dioxide dielectric above said first metal layer includes etching a selected area into the first layer of silicon dioxide dielectric, said vertical air gap having said set height and said set width.

3. The method for implementing vertical airgap structures as recited in claim 1 wherein etching said vertical air gap from said first layer of silicon dioxide dielectric above said first metal layer includes etching said vertical air gap having said set height substantially equal to a thickness of said first layer of silicon dioxide dielectric.

4. The method for implementing vertical airgap structures as recited in claim 1 wherein etching said vertical air gap from said first layer of silicon dioxide dielectric above said first metal layer includes etching said vertical air gap having said set height of approximately one half of a thickness of the first layer of silicon dioxide dielectric.

5. The method for implementing vertical airgap structures as recited in claim 1 wherein etching said vertical air gap from said first layer of silicon dioxide dielectric above said first metal layer includes conventional etching as used for a via opening.

6. The method for implementing vertical airgap structures as recited in claim 1 wherein depositing said second layer of silicon dioxide dielectric and sealing said vertical air gap includes vacuum sealing said vertical air gap with depositing said second layer of silicon dioxide dielectric.

7. The method for implementing vertical airgap structures as recited in claim 1 wherein etching said vertical air gap from said first layer of silicon dioxide dielectric above said first metal layer includes filling said vertical air gap with a sacrificial polymer.

8. The method for implementing vertical airgap structures as recited in claim 7 includes applying a thin porous cap over said filled vertical air gap and said first layer of silicon dioxide dielectric.

9. The method for implementing vertical airgap structures as recited in claim 8 includes applying heat to evaporate said sacrificial polymer from said filled vertical air gap through said thin porous cap.

10. The method for implementing vertical airgap structures as recited in claim 8 wherein etching said via opening through said second and first layers of silicon dioxide dielectric includes etching said via opening through said thin porous cap.

11. A structure for implementing vertical airgap structures between chip metal layers comprising:

a first metal layer;

a first layer of silicon dioxide dielectric disposed on said first metal layer;

a vertical air gap formed in said first layer of silicon dioxide dielectric above said first metal layer; said vertical air gap having a set width substantially equal to a width of a metal signal trace of said first metal layer;

a second layer of silicon dioxide dielectric disposed on said first layer of silicon dioxide dielectric and said vertical air gap;

a next metal layer formed in said second layer of silicon dioxide dielectric and a metal via extending through said second and first layers of silicon dioxide dielectric between said first and second metal layers; said vertical air gap having a set height substantially less than to a distance between said first metal layer and said second metal layer.

12. The structure for implementing vertical airgap structures between chip metal layers as recited in claim 11 wherein said vertical air gap includes a selected area etched into the first layer of silicon dioxide dielectric, said vertical air gap having said set height and said set width.

13. The structure for implementing vertical airgap structures between chip metal layers as recited in claim 11 wherein said vertical air gap has said set height substantially equal to a thickness of said first layer of silicon dioxide dielectric.

14. The structure for implementing vertical airgap structures between chip metal layers as recited in claim 11 wherein said vertical air gap has said set height of approximately one half of a thickness of the first layer of silicon dioxide dielectric.

15. The structure for implementing vertical airgap structures between chip metal layers as recited in claim 11 wherein said vertical air gap is filled with a sacrificial polymer.

16. The structure for implementing vertical airgap structures between chip metal layers as recited in claim 15 includes a thin porous cap extending over said filled vertical air gap and said first layer of silicon dioxide dielectric.

17. The structure for implementing vertical airgap structures between chip metal layers as recited in claim 16 wherein said sacrificial polymer is evaporated from said filled vertical air gap through said thin porous cap by applying heat.

18. The structure for implementing vertical airgap structures between chip metal layers as recited in claim 11 wherein said vertical air gap is vacuum sealed with deposition of said second layer of silicon dioxide dielectric.