Patent Assignment
Reel/Frame 036779/0001
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded: 2015-10-05
Received: 2015-10-05
Pages: 985
Assignors
GLOBALFOUNDRIES U.S. 2 LLC
Executed: 2015-09-10
GLOBALFOUNDRIES U.S. INC.
Executed: 2015-09-10
Assignee
GLOBALFOUNDRIES INC.
PO BOX 309, UGLAND HOUSE, GRAND CAYMAN, KYX, KY1-1104, CAYMAN ISLANDS
Covered Applications
(100)
CONTROLLED METAL EXTRUSION OPENING IN SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING
App. No. 14/718,466
→
FILE SYSTEM LEVEL DATA PROTECTION DURING POTENTIAL SECURITY BREACH
App. No. 14/718,331
→
EMBEDDED ON-CHIP SECURITY
App. No. 14/718,128
→
FACILITATING CHIP DICING FOR METAL-METAL BONDING AND HYBRID WAFER BONDING
App. No. 14/716,959
→
REDUCING WAFER BONDING MISALIGNMENT BY VARYING THERMAL TREATMENT PRIOR TO BONDING
App. No. 14/716,236
→
SUBSTRATE BONDING WITH DIFFUSION BARRIER STRUCTURES
App. No. 14/716,300
→
SILICON-ON-INSULATOR HEAT SINK
App. No. 14/715,693
→
SHALLOW TRENCH ISOLATION STRUCTURES
App. No. 14/714,779
→
CIRCUIT FOR DETECTING STRUCTURAL DEFECTS IN AN INTEGRATED CIRCUIT CHIP, METHODS OF USE AND MANUFACTURE AND DESIGN STRUCTURES
App. No. 14/713,626
→
INTEGRATED SEMICONDUCTOR DEVICES WITH SINGLE CRYSTALLINE BEAM, METHODS OF MANUFACTURE AND DESIGN STRUCTURE
App. No. 14/713,327
→
BACKSIDE INTEGRATION OF RF FILTERS FOR RF FRONT END MODULES AND DESIGN STRUCTURE
App. No. 14/712,092
→
DUAL SHALLOW TRENCH ISOLATION (STI) STRUCTURE FOR FIELD EFFECT TRANSISTOR (FET)
App. No. 14/712,397
→
SPUTTER AND SURFACE MODIFICATION ETCH PROCESSING FOR METAL PATTERNING IN INTEGRATED CIRCUITS
App. No. 14/711,872
→
METHOD OF SELF-CORRECTING POWER GRID FOR SEMICONDUCTOR STRUCTURES
App. No. 14/710,935
→
CHAMFERED CORNER CRACKSTOP FOR AN INTEGRATED CIRCUIT CHIP
App. No. 14/711,109
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SEMICONDUCTOR STRUCTURES WITH PAIR(S) OF VERTICAL FIELD EFFECT TRANSISTORS, EACH PAIR HAVING A SHARED SOURCE/DRAIN REGION AND METHODS OF FORMING THE STRUCTURES
App. No. 14/711,069
→
PROACTIVE RISK ANALYSIS AND GOVERNANCE OF UPGRADE PROCESS
App. No. 14/708,753
→
INTEGRATED CIRCUIT STRUCTURES HAVING OFF-AXIS IN-HOLE CAPACITOR
App. No. 14/708,755
→
BURIED-CHANNEL FIELD-EFFECT TRANSISTORS
App. No. 14/707,775
→
BACK-END TRANSISTORS WITH HIGHLY DOPED LOW-TEMPERATURE CONTACTS
App. No. 14/707,923
→
INDUCING DEVICE VARIATION FOR SECURITY APPLICATIONS
App. No. 14/707,442
→
ENABLING ENHANCED RELIABILITY AND MOBILITY FOR REPLACEMENT GATE PLANAR AND FINFET STRUCTURES
App. No. 14/707,822
→
SOLID STATE NANOPORE DEVICES AND METHODS OF MANUFACTURE
App. No. 14/706,495
→
DETECTION OF FOREIGN MATERIAL ON A SUBSTRATE CHUCK
App. No. 14/705,065
→
HETEROGENEOUS INTEGRATION OF GROUP III NITRIDE ON SILICON FOR ADVANCED INTEGRATED CIRCUITS
App. No. 14/705,425
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ON-CHIP DIODE WITH FULLY DEPLETED SEMICONDUTOR DEVICES
App. No. 14/705,397
→
REDUNDANT VIA STRUCTURE FOR METAL FUSE APPLICATIONS
App. No. 14/702,794
→
SILVER ALLOYING POST-CHIP JOIN
App. No. 14/702,984
→
LATERAL-DIMENSION-REDUCING METALLIC HARD MASK ETCH
App. No. 14/701,605
→
PROVIDING ACCESS CONTROL FOR PUBLIC AND PRIVATE DOCUMENT FIELDS
App. No. 14/701,910
→
MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER
App. No. 14/701,371
→
AXIOCENTRIC SCRUBBING LAND GRID ARRAY CONTACTS AND METHODS FOR FABRICATION
App. No. 14/700,850
→
INTEGRATED CIRCUIT WITH ON CHIP PLANAR DIODE AND CMOS DEVICES
App. No. 14/700,147
→
INTELLIGENT WARDROBE PROGRAM
App. No. 14/700,254
→
ON-CHIP USABLE LIFE DEPLETION METER AND ASSOCIATED METHOD
App. No. 14/700,402
→
TUNABLE FILTER STRUCTURES AND DESIGN STRUCTURES
App. No. 14/700,744
→
TAPE HEAD WITH THERMAL TAPE-HEAD DISTANCE SENSOR
App. No. 14/699,580
→
SERIES-CONNECTED NANOWIRE STRUCTURES
App. No. 14/699,034
→
FABRICATION OF FIELD-EFFECT TRANSISTORS WITH ATOMIC LAYER DOPING
App. No. 14/699,859
→
ALTERNATE DUAL DAMASCENE METHOD FOR FORMING INTERCONNECTS
App. No. 14/698,948
→
PHOTODETECTOR AND METHODS OF MANUFACTURE
App. No. 14/699,015
→
Self-Aligned III-V MOSFET Fabrication With In-Situ III-V Epitaxy And In-Situ Metal Epitaxy and Contact Formation
App. No. 14/697,991
→
WAVELENGTH DIVISION MULTIPLEXING WITH MULTI-CORE FIBER
App. No. 14/696,843
→
MOSFET WITH WORK FUNCTION ADJUSTED METAL BACKGATE
App. No. 14/696,736
→
MOSFET WITH WORK FUNCTION ADJUSTED METAL BACKGATE
App. No. 14/696,693
→
A MANUFACTURING PROCESS FOR FINFET DEVICE
App. No. 14/696,605
→
FINFET DEVICE
App. No. 14/696,534
→
ELECTRONIC FUSE WITH RESISTIVE HEATER
App. No. 14/695,113
→
DIRECTED SURFACE FUNCTIONALIZATION ON SELECTED SURFACE AREAS OF TOPOGRAPHICAL FEATURES WITH NANOMETER RESOLUTION
App. No. 14/695,215
→
SYSTEMS AND METHODS FOR CONTROLLING INTEGRATED CIRCUIT CHIP TEMPERATURE USING TIMING CLOSURE-BASED ADAPTIVE FREQUENCY SCALING
App. No. 14/695,091
→
PRE-TEST POWER-OPTIMIZED BIN REASSIGNMENT FOLLOWING SELECTIVE VOLTAGE BINNING
App. No. 14/695,112
→
DOUBLE MIRROR STRUCTURE FOR WAVELENGTH DIVISION MULTIPLEXING WITH POLYMER WAVEGUIDES
App. No. 14/696,034
→
BURIED WAVEGUIDE PHOTODETECTOR
App. No. 14/694,265
→
BOOSTING DECOMPRESSION IN THE PRESENCE OF REOCCURRING HUFFMAN TREES
App. No. 14/694,831
→
DYNAMIC RECONFIGURATION-SWITCHING OF WINDINGS IN AN ELECTRIC MOTOR USED AS A GENERATOR IN AN ELECTRIC VEHICLE
App. No. 14/694,838
→
HIGH DENSITY CAPACITOR STRUCTURE AND METHOD
App. No. 14/692,881
→
FORMATION OF METAL NANOSPHERES AND MICROSPHERES
App. No. 14/691,326
→
Laser Doping of Crystalline Semiconductors Using a Dopant-Containing Amorphous Silicon Stack for Dopant Source and Passivation
App. No. 14/691,124
→
ALTERNATING OPEN-ENDED VIA CHAINS FOR TESTING VIA FORMATION AND DIELECTRIC INTEGRITY
App. No. 14/689,463
→
THICK BOND PAD FOR CHIP WITH CAVITY PACKAGE
App. No. 14/688,215
→
OVERLAY-TOLERANT VIA MASK AND REACTIVE ION ETCH (RIE) TECHNIQUE
App. No. 14/688,027
→
ALTERING CAPACITANCE OF MIM CAPACITOR HAVING REACTIVE LAYER THEREIN
App. No. 14/687,049
→
BARRIER TRENCH STRUCTURE AND METHODS OF MANUFACTURE
App. No. 14/686,972
→
WHOLE WAFER EDGE SEAL
App. No. 14/686,904
→
ON CHIP ANTENNA WITH OPENING
App. No. 14/687,002
→
CHARGE SENSORS USING INVERTED LATERAL BIPOLAR JUNCTION TRANSISTORS
App. No. 14/687,489
→
DATA STORAGE TAPE WITH RANDOM ACCESS DATA
App. No. 14/687,050
→
Automatic Analytical Cloud Scaling of Hardware Using Resource Sub-Cloud
App. No. 14/685,736
→
SEPARATING BONDED WAFERS
App. No. 14/685,973
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METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING SOURCE/DRAIN EPITAXIAL OVERGROWTH FOR FORMING SELF-ALIGNED CONTACTS WITHOUT SPACER LOSS AND A SEMICONDUCTOR DEVICE FORMED BY SAME
App. No. 14/686,260
→
ELECTRONIC PACKAGE THAT INCLUDES A PLURALITY OF INTEGRATED CIRCUIT DEVICES BONDED IN A THREE-DIMENSIONAL STACK ARRANGEMENT
App. No. 14/685,061
→
DEEP TRENCH CAPACITOR
App. No. 14/684,533
→
SPLIT FLEX CABLE
App. No. 14/683,995
→
ENGINEERING MULTIPLE THRESHOLD VOLTAGES IN AN INTEGRATED CIRCUIT
App. No. 14/681,215
→
DEFECT REDUCTION WITH ROTATED DOUBLE ASPECT RATIO TRAPPING
App. No. 14/680,328
→
FINFET STRUCTURES HAVING SILICON GERMANIUM AND SILICON CHANNELS
App. No. 14/678,024
→
BIPOLAR JUNCTION TRANSISTORS WITH SELF-ALIGNED TERMINALS
App. No. 14/677,303
→
PREDICTING PROCESS FAIL LIMITS
App. No. 14/674,571
→
LIQUID CRYSTAL INTEGRATED CIRCUIT AND METHOD TO FABRICATE SAME
App. No. 14/674,242
→
MAINTAINING A CLUSTER OF VIRTUAL MACHINES
App. No. 14/673,926
→
FORMATION OF A HIGH ASPECT RATIO TRENCH IN A SEMICONDUCTOR SUBSTRATE AND A BIPOLAR SEMICONDUCTOR DEVICE HAVING A HIGH ASPECT RATIO TRENCH ISOLATION REGION
App. No. 14/673,958
→
ANONYMOUS VEHICLE COMMUNICATION PROTOCOL IN VEHICLE-TO-VEHICLE NETWORKS
App. No. 14/674,859
→
HIGH VOLTAGE LATERAL DOUBLE-DIFFUSED METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (LDMOSFET) HAVING A DEEP FULLY DEPLETED DRAIN DRIFT REGION
App. No. 14/672,865
→
VIA LEAKAGE AND BREAKDOWN TESTING
App. No. 14/673,185
→
FINFET STRUCTURES HAVING SILICON GERMANIUM AND SILICON FINS
App. No. 14/672,160
→
FINFET STRUCTURES HAVING SILICON GERMANIUM AND SILICON FINS
App. No. 14/672,157
→
HIGH DENSITY TIMING BASED SERVO FORMAT FOR USE WITH TILTED TRANSDUCER ARRAYS
App. No. 14/671,819
→
THERMAL HOT SPOT COOLING FOR SEMICONDUCTOR DEVICES
App. No. 14/669,775
→
MEMORY CELLS WITH READ ACCESS SCHEMES
App. No. 14/669,043
→
METHOD OF FORMING A GLASS INTERPOSER WITH THERMAL VIAS
App. No. 14/668,031
→
GLASS INTERPOSER WITH EMBEDDED THERMOELECTRIC DEVICES
App. No. 14/668,017
→
DENSE FINFET SRAM
App. No. 14/668,018
→
SILICON-ON-NOTHING FINFETS
App. No. 14/666,469
→
TAPE HEAD WITH TAPE-BEARING SURFACE EXHIBITING AN ARRAY OF PROTRUDING TOPOGRAPHIC FEATURES
App. No. 14/666,590
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LIQUID CRYSTAL INTEGRATED CIRCUIT AND METHOD TO FABRICATE SAME
App. No. 14/665,432
→
Process for Forming a Surrounding Gate for a Nanowire Using a Sacrificial Patternable Dielectric
App. No. 14/664,435
→
DOUBLE SOLDER BUMPS ON SUBSTRATES FOR LOW TEMPERATURE FLIP CHIP BONDING
App. No. 14/663,806
→
METHOD TO FABRICATE COPPER WIRING STRUCTURES AND STRUCTURES FORMED THEREBY
App. No. 14/664,036
→
DOUBLE SOLDER BUMPS ON SUBSTRATES FOR LOW TEMPERATURE FLIP CHIP BONDING
App. No. 14/663,754
→
Fabricating Shallow-Trench Isolation Semiconductor Devices To Reduce Or Eliminate Oxygen Diffusion
App. No. 14/662,743
→