Silicon-on-nothing FinFETs
A semiconductor device includes an insulator formed within a void to electrically isolate an active fin from an underlying substrate. The void is created by removing a sacrificial portion formed between the substrate and the active fin. The sacrificial portion may be doped to allow for a greater thickness relative to an un-doped portion of substantially similar composition. The doped sacrificial portion thickness may be between 10 nm and 250 nm. The thicker sacrificial portion allows for a thicker insulator so as to provide adequate electrical isolation between the active fin and the substrate. During formation of the void, the active fin may be supported by a gate. The semiconductor structure may also include a bulk region that has at least a maintained portion of the sacrificial portion material.
1. A method of fabricating a semiconductor device, the method comprising:
forming an sacrificial portion upon a substrate;
forming a fin portion upon the sacrificial portion;
creating a void by removing the sacrificial portion between the substrate and the fin portion, and;
forming an insulator within the void, the insulator electrically isolating the fin portion from the substrate,
wherein the sacrificial portion is doped to allow for a thicker sacrificial portion relative to an un-doped sacrificial portion of substantially similar composition.
2. The method of claim 1 , wherein forming a fin portion further comprises:
forming epitaxial silicon portion on the sacrificial portion.
3. The method of claim 1 further comprising:
forming a gate to support the fin portion prior to creating the void.
4. The method of claim 1 wherein the doped sacrificial layer has a thickness between 10 and 250 nm.
5. The method of claim 2 further comprising:
patterning an epitaxial sacrificial layer and an epitaxial silicon layer to form the fin portion and the sacrificial portion.
6. The method of claim 5 further comprising:
maintaining a segment of the sacrificial layer in a bulk region.
7. A semiconductor device comprising:
a replacement insulator fin portion within a void between an active fin portion and a substrate that electrically isolates the active fin portion from the substrate, wherein the void is created by removing a sacrificial fin portion; and
a gate over the active fin portion, wherein the gate is a dummy gate.
8. The semiconductor device of claim 7 , wherein the active fin portion is an epitaxially grown silicon portion.
9. The semiconductor device of claim 7 , wherein sacrificial fin portion is doped to allow for a thicker sacrificial fin portion relative to an un-doped sacrificial fin portion of substantially similar composition.
10. The semiconductor device of claim 7 , wherein the sacrificial fin portion has a thickness between 10 and 250 nm.
11. The semiconductor device of claim 7 , further comprising:
a bulk region comprising a maintained portion of doped sacrificial material associated with the sacrificial fin portion.
12. A design structure embodied in a machine readable storage medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:
a replacement insulator fin portion within a void between an active fin portion and a substrate that electrically isolates the active fin portion from the substrate, wherein the void is created by removing a sacrificial fin portion.
13. The design structure of claim 12 , wherein the active fin portion is an epitaxially grown silicon portion.
14. The design structure of claim 12 , further comprising a gate over the active fin portion.
15. The design structure of claim 12 , wherein the sacrificial fin portion has a thickness between 10 and 250 nm.
16. The design structure of claim 12 , further comprising:
a bulk region comprising a maintained portion of doped sacrificial material associated with the sacrificial fin portion.
17. The design structure of claim 14 , wherein the gate is a dummy gate.