Patent Assignment
Reel/Frame 049669/0749
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded: 2019-07-02
Received: 2019-07-02
Pages: 21
Assignor
GLOBALFOUNDRIES INC.
Executed: 2018-11-26
Assignee
ALSEPHINA INNOVATIONS INC.
303 TERRY FOX DRIVE, SUITE 300, OTTAWA, CAX, K2K 3J1, CANADA
Covered Applications
(100)
PHOTODETECTOR AND METHODS OF MANUFACTURE
App. No. 15/594,951
→
SEMICONDUCTOR STRUCTURE INCLUDING A FIRST TRANSISTOR AND A SECOND TRANSISTOR
App. No. 15/467,305
→
INTEGRATED CIRCUITS WITH SPACER CHAMFERING AND METHODS OF SPACER CHAMFERING
App. No. 15/443,522
→
FIELD EFFECT TRANSISTORS HAVING MULTIPLE EFFECTIVE WORK FUNCTIONS
App. No. 15/338,894
→
ON-CHIP FINFET STRUCTURES TO IMPLEMENT PHYSICAL UNCLONABLE FUNCTION FOR SECURITY APPLICATION
App. No. 15/230,632
→
METHODS OF FORMING FINFET DEVICES WITH SUBSTANTIALLY UNDOPED CHANNEL REGIONS
App. No. 15/215,921
→
METHODS OF FORMING SELF-ALIGNED CONTACTS ON FINFET DEVICES
App. No. 15/214,670
→
DEVICES AND METHODS OF FORMING EPI FOR AGGRESSIVE GATE PITCH
App. No. 15/210,012
→
METHOD OF FORMING SELF-ALIGNED METAL LINES AND VIAS
App. No. 15/202,949
→
FINFET CONFORMAL JUNCTION AND HIGH EPI SURFACE DOPANT CONCENTRATION METHOD AND DEVICE
App. No. 15/189,079
→
MOISTURE AND/OR ELECTRICALLY CONDUCTIVE REMAINS DETECTION FOR WAFERS AFTER RINSE / DRY PROCESS
App. No. 15/180,392
→
FINFET CONFORMAL JUNCTION AND ABRUPT JUNCTION WITH REDUCED DAMAGE METHOD AND DEVICE
App. No. 15/180,312
→
BULK FINFET WITH PARTIAL DIELECTRIC ISOLATION FEATURING A PUNCH-THROUGH STOPPING LAYER UNDER THE OXIDE
App. No. 15/176,073
→
MIS (METAL-INSULATOR-SEMICONDUCTOR) CONTACT STRUCTURES FOR SEMICONDUCTOR DEVICES
App. No. 15/167,306
→
METHOD OF ADJUSTING SPACER THICKNESS TO PROVIDE VARIABLE THRESHOLD VOLTAGES IN FINFETS
App. No. 15/156,822
→
SELF-ALIGNED VIA AND AIR GAP
App. No. 15/155,569
→
RAISED FIN STRUCTURES AND METHODS OF FABRICATION
App. No. 15/154,444
→
METHODS OF FORMING PUNCH THROUGH STOP REGIONS ON FINFET DEVICES ON CMOS-BASED IC PRODUCTS USING DOPED SPACERS
App. No. 15/142,052
→
FORMATION OF IC STRUCTURE WITH PAIR OF UNITARY METAL FINS
App. No. 15/140,808
→
THIN STRAIN RELAXED BUFFERS WITH MULTILAYER FILM STACKS
App. No. 15/133,683
→
FORMING UNIFORM WF METAL LAYERS IN GATE AREAS OF NANO-SHEET STRUCTURES
App. No. 15/093,952
→
NOVEL INTEGRATION PROCESS TO FORM MICROELECTRONIC OR MICROMECHANICAL STRUCTURES
App. No. 15/088,592
→
VISUALIZATION OF ALIGNMENT MARKS ON A CHIP COVERED BY A PRE-APPLIED UNDERFILL
App. No. 15/081,403
→
METHOD OF FORMING SELF ALIGNED CONTINUITY BLOCKS FOR MANDREL AND NON-MANDREL INTERCONNECT LINES
App. No. 15/077,564
→
METHOD FOR PRODUCING SELF-ALIGNED VIAS
App. No. 15/071,247
→
METHODS FOR FORMING FinFETS HAVING A CAPPING LAYER FOR REDUCING PUNCH THROUGH LEAKAGE
App. No. 15/060,052
→
PROCESS MONITORING FOR GATE CUT MASK
App. No. 15/055,954
→
METHODS OF FORMING SPACERS ON FINFET DEVICES
App. No. 15/047,018
→
FIELD-EFFECT TRANSISTORS WITH SOURCE/DRAIN REGIONS OF REDUCED TOPOGRAPHY
App. No. 15/043,917
→
INTEGRATED CIRCUIT HAVING IMPROVED ELECTROMIGRATION PERFORMANCE AND METHOD OF FORMING SAME
App. No. 15/041,203
→
CONFORMAL BUFFER LAYER IN SOURCE AND DRAIN REGIONS OF FIN-TYPE TRANSISTORS
App. No. 15/040,477
→
METHODS OF FORMING STRAINED CHANNEL REGIONS ON FINFET DEVICES BY PERFORMING A HEATING PROCESS ON A HEAT-EXPANDABLE MATERIAL
App. No. 15/012,184
→
SEMICONDUCTOR DEVICE INCLUDING EMBEDDED CRYSTALLINE BACK-GATE BIAS PLANES, RELATED DESIGN STRUCTURE AND METHOD OF FABRICATION
App. No. 15/009,906
→
UNIFORM DEPTH FIN TRENCH FORMATION
App. No. 15/007,494
→
INCREASED SURFACE AREA OF EPITAXIAL STRUCTURES IN A MIXED N/P TYPE SEMICONDUCTOR STRUCTURE WITH MULTIPLE EPITAXIAL HEADS
App. No. 15/002,000
→
SEMICONDUCTOR CHARGE PUMP WITH IMBEDDED CAPACITOR
App. No. 14/995,324
→
DIMENSION-CONTROLLED VIA FORMATION PROCESSING
App. No. 14/969,154
→
PROFILE CONTROL OVER A COLLECTOR OF A BIPOLAR JUNCTION TRANSISTOR
App. No. 14/968,286
→
DIELECTRIC COVER FOR A THROUGH SILICON VIA
App. No. 14/967,965
→
FLEXIBLE ACTIVE MATRIX DISPLAY
App. No. 14/966,161
→
SEMICONDUCTOR STRUCTURE INCLUDING A NONVOLATILE MEMORY CELL AND METHOD FOR THE FORMATION THEREOF
App. No. 14/959,382
→
DEVICE RESULTING FROM PRINTING MINIMUM WIDTH SEMICONDUCTOR FEATURES AT NON-MINIMUM PITCH
App. No. 14/953,864
→
FINFET DEVICES COMPRISING A DIELECTRIC LAYER/CMP STOP LAYER/HARDMASK/ETCH STOP LAYER/GAP-FILL MATERIAL STACK
App. No. 14/949,481
→
FINFET FABRICATION BY FORMING ISOLATION TRENCHES PRIOR TO FIN FORMATION
App. No. 14/941,885
→
SEMICONDUCTOR STRUCTURE HAVING A SOURCE AND A DRAIN WITH REVERSE FACETS
App. No. 14/937,029
→
METHODS TO THIN DOWN RMG SIDEWALL LAYERS FOR SCALABILITY OF GATE-LAST PLANAR CMOS AND FINFET TECHNOLOGY
App. No. 14/935,676
→
METHODS FOR CIRCUIT PATTERN LAYOUT DECOMPOSITION
App. No. 14/930,949
→
INTEGRATED CIRCUIT PRODUCT COMPRISING LATERAL AND VERTICAL FINFET DEVICES
App. No. 14/931,409
→
GATE STACK AND CONTACT STRUCTURE
App. No. 14/924,925
→
METHODS OF MAKING A SELF-ALIGNED CHANNEL DRIFT DEVICE
App. No. 14/922,308
→
SEMICONDUCTOR STRUCTURE HAVING GAP FILL DIELECTRIC LAYER DISPOSED BETWEEN FINS
App. No. 14/918,012
→
METHODS OF FORMING STRESSED CHANNEL REGIONS FOR A FINFET SEMICONDUCTOR DEVICE AND THE RESULTING DEVICE
App. No. 14/883,049
→
METHODS OF FORMING TRANSISTOR STRUCTURES INCLUDING FORMING CHANNEL MATERIAL AFTER FORMATION PROCESSES TO PREVENT DAMAGE TO THE CHANNEL MATERIAL
App. No. 14/883,045
→
FORMING INTERCONNECT FEATURES WITH REDUCED SIDEWALL TAPERING
App. No. 14/876,023
→
METHOD FOR CREATING METAL GATE RESISTOR IN FDSOL AND RESULTING DEVICE
App. No. 14/872,294
→
METHOD FOR CREATING SELF-ALIGNED SDB FOR MINIMUM GATE-JUNCTION PITCH AND EPITAXY FORMATION IN A FIN-TYPE IC DEVICE
App. No. 14/858,412
→
METHOD AND PROCESS FOR INTEGRATION OF TSV-MIDDLE IN 3D IC STACKS
App. No. 14/858,373
→
METHODS OF FORMING REDUCED THICKNESS SPACERS IN CMOS BASED INTEGRATED CIRCUIT PRODUCTS
App. No. 14/845,499
→
INTEGRATED CIRCUITS INCLUDING A MIMCAP DEVICE AND METHODS OF FORMING THE SAME FOR LONG AND CONTROLLABLE RELIABILITY LIFETIME
App. No. 14/835,278
→
EARLY PTS WITH BUFFER FOR CHANNEL DOPING CONTROL
App. No. 14/826,803
→
METHOD FOR IMPROVED FIN PROFILE
App. No. 14/812,653
→
DIELECTRIC FILLER FINS FOR PLANAR TOPOGRAPHY IN GATE LEVEL
App. No. 14/808,914
→
METHODS OF FORMING DOPED TRANSITION REGIONS OF TRANSISTOR STRUCTURES
App. No. 14/805,907
→
METHOD INCLUDING A FORMATION OF A TRANSISTOR AND SEMICONDUCTOR STRUCTURE INCLUDING A FIRST TRANSISTOR AND A SECOND TRANSISTOR
App. No. 14/805,827
→
GATE STRUCTURES FOR TRANSISTOR DEVICES FOR CMOS APPLICATIONS AND PRODUCTS
App. No. 14/793,005
→
BASE PROFILE OF SELF-ALIGNED BIPOLAR TRANSISTORS FOR POWER AMPLIFIER APPLICATIONS
App. No. 14/755,862
→
METHODS INCLUDING A PROCESSING OF WAFERS AND SPIN COATING TOOL
App. No. 14/753,198
→
METHOD TO PROTECT MOL METALLIZATION FROM HARDMASK STRIP PROCESS
App. No. 14/752,210
→
INDUCTION HEATING FOR UNDERFILL REMOVAL AND CHIP REWORK
App. No. 14/741,757
→
Method and Structure to Reduce FET Threshold Voltage Shift Due to Oxygen Diffusion
App. No. 14/741,618
→
PRINTED TRANSISTOR AND FABRICATION METHOD
App. No. 14/741,169
→
BULK SEMICONDUCTOR FINS WITH SELF-ALIGNED SHALLOW TRENCH ISOLATION STRUCTURES
App. No. 14/735,466
→
PASSIVATION LAYER TOPOGRAPHY
App. No. 14/734,600
→
BREAKDOWN VOLTAGE MULTIPLYING INTEGRATION SCHEME
App. No. 14/732,680
→
GATE HEIGHT UNIFORMITY IN SEMICONDUCTOR DEVICES
App. No. 14/730,887
→
FABRICATION METHODS FOR MULTI-LAYER SEMICONDUCTOR STRUCTURES
App. No. 14/730,614
→
10 NM ALTERNATIVE N/P DOPED FIN FOR SSRW SCHEME
App. No. 14/727,143
→
METHODS OF FORMING REPLACEMENT FINS FOR A FINFET DEVICE
App. No. 14/727,364
→
CONTROLLED METAL EXTRUSION OPENING IN SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING
App. No. 14/718,466
→
EMBEDDED ON-CHIP SECURITY
App. No. 14/718,128
→
DEVICE AND METHOD FOR FABRICATING THIN SEMICONDUCTOR CHANNEL AND BURIED STRAIN MEMORIZATION LAYER
App. No. 14/717,551
→
SUBSTRATE BONDING WITH DIFFUSION BARRIER STRUCTURES
App. No. 14/716,300
→
BLANKET EPI SUPER STEEP RETROGRADE WELL FORMATION WITHOUT Si RECESS
App. No. 14/716,045
→
METHOD AND STRUCTURE TO MAKE FINS WITH DIFFERENT FIN HEIGHTS AND NO TOPOGRAPHY
App. No. 14/712,462
→
CHAMFERED CORNER CRACKSTOP FOR AN INTEGRATED CIRCUIT CHIP
App. No. 14/711,109
→
INDUCING DEVICE VARIATION FOR SECURITY APPLICATIONS
App. No. 14/707,442
→
2D SELF-ALIGNED VIA FIRST PROCESS FLOW
App. No. 14/707,443
→
DETECTION OF FOREIGN MATERIAL ON A SUBSTRATE CHUCK
App. No. 14/705,065
→
SEMICONDUCTOR STRUCTURE HAVING LOGIC REGION AND ANALOG REGION
App. No. 14/700,748
→
ALTERNATE DUAL DAMASCENE METHOD FOR FORMING INTERCONNECTS
App. No. 14/698,948
→
PHOTODETECTOR AND METHODS OF MANUFACTURE
App. No. 14/699,015
→
BLOCK LEVEL PATTERNING PROCESS
App. No. 14/699,122
→
METHOD FOR CREATING SELF-ALIGNED COMPACT CONTACTS IN AN IC DEVICE MEETING FABRICATION SPACING CONSTRAINTS
App. No. 14/696,684
→
METHODS FOR FABRICATING INTEGRATED CIRCUITS USING DIRECTED SELF-ASSEMBLY CHEMOEPITAXY
App. No. 14/692,359
→
BARRIER TRENCH STRUCTURE AND METHODS OF MANUFACTURE
App. No. 14/686,972
→
INTERPOSER AND METHODS OF FORMING AND TESTING AN INTERPOSER
App. No. 14/684,664
→
INTEGRATED CIRCUITS WITH SPACER CHAMFERING AND METHODS OF SPACER CHAMFERING
App. No. 14/681,428
→
FINFET CONFORMAL JUNCTION AND ABRUPT JUNCTION WITH REDUCED DAMAGE METHOD AND DEVICE
App. No. 14/679,074
→
FINFET STRUCTURES HAVING SILICON GERMANIUM AND SILICON CHANNELS
App. No. 14/678,024
→
FINFET CONFORMAL JUNCTION AND HIGH EPI SURFACE DOPANT CONCENTRATION METHOD AND DEVICE
App. No. 14/676,912
→