Methods of forming spacers on FinFET devices
View Patent ↗One illustrative method disclosed herein includes forming a liner layer above a layer of spacer material, forming an ion-containing region in at least a portion of a first portion of the liner layer while not forming the ion-containing region in a second portion of the liner layer, performing a liner etching process on the first and second portions of the liner layer so as to remove the second portion of the liner layer while leaving at least a portion of the first portion of the liner layer positioned adjacent a gate structure and, with the first portion of the liner layer positioned adjacent the gate structure, performing at least one spacer formation anisotropic etching process on the layer of spacer material so as to define a spacer adjacent the gate structure.
1. A method of forming a spacer for a FinFET device, comprising:
forming a layer of spacer material above a gate structure and above a fin;
forming a liner layer above said layer of spacer material, said liner layer having a first portion positioned around said gate structure and a second portion positioned around said fin:
forming an ion-containing region in at least a portion of said first portion of said liner layer while not forming said ion-containing region in said second portion of said liner layer;
performing a liner etching process on said first and second portions of said liner layer so as to remove said second portion of said liner layer while leaving at least a portion of said first portion of said liner layer positioned adjacent said gate structure; and
with said first portion of said liner layer positioned adjacent said gate structure, performing at least one spacer formation anisotropic etching process on said layer of spacer material so as to define a spacer adjacent said gate structure.
2. The method of claim 1 , wherein forming said ion-containing region comprises performing an ion implantation process.
3. The method of claim 1 , wherein forming said ion-containing region comprises performing a plasma-based process so as to introduce ions into said first portion of said liner layer.
4. The method of claim 1 , wherein forming said ion-containing region comprises forming said ion-containing region such that said ion-containing region has a concentration of introduced ions of about 4e 2 ion/cm 3 .
5. The method of claim 4 , wherein said introduced ions comprise one of silicon, carbon, germanium, fluorine or chlorine.
6. The method of claim 1 , wherein the presence of said ion-containing region in said first portion of said liner layer causes said first portion of said liner layer to have a slower etch rate than that of said second portion of said liner layer.
7. The method of claim 1 , wherein forming said ion-containing region in at least a portion of said first portion of said liner layer while not forming said ion-containing region in said second portion of said liner layer comprises:
forming a masking layer that exposes said first portion of said liner layer while masking said second portion of said liner layer; and
with said masking layer in position, performing at least one ion introduction process operation to form said ion-containing region in at least a portion of said exposed first portion of said liner layer.
8. The method of claim 1 , wherein said first portion of said liner layer is positioned above a top surface and adjacent opposite side surfaces of a gate cap positioned above said gate structure.
9. The method of claim 1 , wherein said first portion of said liner layer is positioned only above a substantially planar surface of said layer of spacer material.
10. The method of claim 1 , wherein said ion-containing region extends throughout an entire thickness of said first portion of said liner layer.
11. The method of claim 10 , wherein said ion-containing region further extends into said layer of spacer material.
12. The method of claim 11 , wherein said ion-containing region further extends into a gate cap positioned above said gate structure.
13. The method of claim 12 , wherein said gate structure is one of a sacrificial gate structure or a final gate structure for said FinFET device.
14. A method of forming a spacer for a FinFET device, comprising:
forming a fin in a semiconductor substrate;
forming a gate structure above said fin;
forming a layer of spacer material above said gate structure and above said fin;
forming a liner layer above said layer of spacer material;
forming a masking layer above said fin and adjacent said gate structure, wherein said masking layer exposes a first portion of said liner layer adjacent said gate structure and masks a second portion of said liner layer positioned above said fin;
with said masking layer in position above said fin, performing at least one ion introduction process operation to form an ion-containing region in at least a portion of said exposed first portion of said liner layer;
removing said masking layer;
performing a liner etching process on said first and second portions of said liner layer so as to remove said second portion of said liner layer while leaving at least a portion of said first portion of said liner layer positioned adjacent said gate structure; and
with said first portion of said liner layer positioned adjacent said gate structure, performing at least one spacer formation anisotropic etching process on said layer of spacer material so as to define a spacer adjacent said gate structure.
15. The method of claim 14 , wherein performing said at least one ion introduction process operation comprises performing an ion implantation process.
16. The method of claim 14 , wherein performing said at least one ion introduction process operation comprises performing a plasma-based process so as to introduce ions into said first portion of said liner layer.
17. The method of claim 15 , wherein said ion-containing region has a concentration of introduced ions of about 4e 2 ion/cm 3 .
18. The method of claim 17 , wherein said introduced ions comprise one of silicon, carbon, germanium, fluorine or chlorine.
19. The method of claim 14 , wherein the presence of said ion-containing region in said first portion of said liner layer causes said first portion of said liner layer to have a slower etch rate than that of said second portion of said liner layer.
20. The method of claim 14 , wherein said first portion of said liner layer is positioned above a top surface and adjacent opposite side surfaces of a gate cap positioned above said gate structure.
21. The method of claim 14 , wherein said first portion of said liner layer is positioned only above a substantially planar surface of said layer of spacer material.
22. The method of claim 14 , wherein said ion-containing region extends throughout an entire thickness of said first portion of said liner layer.
23. The method of claim 22 , wherein said ion-containing region further extends into said layer of spacer material.
24. The method of claim 23 , wherein said ion-containing region further extends into a gate cap positioned above said gate structure.