Semiconductor structure having gap fill dielectric layer disposed between fins
View Patent ↗Embodiments of the present invention provide methods of removing fin portions from a finFET. At a starting point, a high-K dielectric layer is disposed on a substrate. A fin hardmask and lithography stack is deposited on the high-k dielectric. A fin hardmask is exposed, and a first portion of the fin hardmark is removed. The lithography stack is removed. A second portion of the fin hardmask is removed. Fins are formed. A gap fill dielectric is deposited and recessed.
1. A semiconductor structure, comprising:
a substrate having a first portion and a second portion;
a plurality of fins disposed on the substrate in the first portion and not disposed on the substrate in a plurality of second portions, wherein the second portions each have a width less than twice a fin pitch and do not comprise an over-etch substrate portion; and
a gap fill dielectric layer disposed on the substrate in the second portion and between the fins in the first portion, wherein a surface of the gap fill dielectric layer is below a top of the plurality of fins.
2. The semiconductor structure of claim 1 , wherein the substrate comprises a silicon wafer.
3. The semiconductor structure of claim 1 , wherein the gap fill dielectric layer comprises a flowable oxide.
4. The semiconductor structure of claim 3 , wherein the flowable oxide is a self-planarizing material.
5. The semiconductor structure of claim 3 , wherein the gap fill dielectric layer is deposited by a chemical vapor deposition (CVD) process.
6. A semiconductor structure, comprising:
a substrate having a first portion and a second portion;
a plurality of fins disposed on the substrate in the first portion and not disposed on the substrate in a plurality of second portions wherein each the second portions do not comprise an over-etch substrate portion, wherein each fin of the plurality of fins has a lower width greater than a middle width and an upper width the same as the middle width; and
a gap fill dielectric layer disposed on the substrate in the second portion and between the fins in the first portion, wherein a surface of the gap fill dielectric layer is below a top of the plurality of fins;
wherein the semiconductor structure is formed by a process, comprising:
depositing a high-K dielectric layer on the substrate;
forming a plurality of fin hardmask regions disposed on the dielectric layer;
depositing a lithography stack on the semiconductor structure;
performing a first etch into the lithography stack to expose a portion of at least one fin hardmask region, the hardmask region being comprised of a first hardmask portion disposed on a second hardmask portion, wherein a subset of fin hardmask regions remain covered by the lithography stack;
performing a second etch to remove the first hardmask portion of the exposed hardmask region;
removing the lithography stack;
performing a third etch to remove the second hardmask portion of the exposed hardmask region;
performing a substrate recess to form fins at locations of the subset of fin hardmask regions that remain covered by the lithography stack;
removing the subset of fin hardmask regions;
depositing the gap fill dielectric layer; and
recessing the gap fill dielectric layer.
7. The semiconductor structure of claim 6 , wherein the substrate comprises a silicon wafer.
8. The semiconductor structure of claim 6 , wherein the gap fill dielectric layer comprises a flowable oxide.
9. The semiconductor structure of claim 8 , wherein the flowable oxide is a self-planarizing material.
10. The semiconductor structure of claim 8 , wherein depositing the gap fill dielectric layer comprises a chemical vapor deposition (CVD) process.
11. The semiconductor structure of claim 6 , wherein the depositing a high-K dielectric layer comprises depositing aluminum oxide.
12. The semiconductor structure of claim 6 , wherein the depositing a high-K dielectric layer comprises depositing hafnium oxide.
13. The semiconductor structure of claim 6 , wherein the depositing a lithography stack comprises:
depositing a carbon layer on the high-K dielectric layer and fin hardmask regions;
depositing a nitride layer on the carbon layer; and
depositing a photoresist layer on the nitride layer.
14. The semiconductor structure of claim 6 , wherein the performing a first etch into the lithography stack to expose a portion of at least one fin hardmask region comprises performing a reactive ion etch.
15. The semiconductor structure of claim 6 , wherein the performing a second etch to remove the first hardmask portion of the exposed hardmask region comprises performing an isotropic etch.
16. The semiconductor structure of claim 6 , wherein the performing a third etch to remove the second hardmask portion of the exposed hardmask region comprises performing an anisotropic etch.
17. A semiconductor structure, comprising:
a substrate having a first portion and a second portion;
a plurality of fins disposed on the substrate in the first portion and not disposed on the substrate in the second portion, wherein each fin of the plurality of fins has a lower width greater than a middle width and an upper width the same as the middle width, and a plurality of second portions each having a width less than twice a fin pitch and do not contain an over-etch substrate portion; and
a gap fill dielectric layer disposed on the substrate in the second portion and between the fins in the first portion, wherein a surface of the gap fill dielectric layer is below a top of the plurality of fins;
wherein the semiconductor structure is formed by a process, comprising:
depositing an aluminum oxide dielectric layer on the substrate;
forming a plurality of fin hardmask regions disposed on the dielectric layer;
depositing a lithography stack on the semiconductor structure;
performing a first etch into the lithography stack to expose a portion of at least one fin hardmask region, the hardmask region being comprised of a silicon nitride portion disposed on a silicon oxide portion, wherein a subset of fin hardmask regions remain covered by the lithography stack;
performing a second etch to remove the silicon nitride portion of the exposed hardmask region;
removing the lithography stack;
performing a third etch to remove the silicon oxide portion of the exposed hardmask region;
performing a substrate recess to form fins at locations of the subset of fin hardmask regions that remain covered by the lithography stack;
removing the subset of fin hardmask regions;
depositing the gap fill dielectric layer; and
recessing the gap fill dielectric layer.
18. The semiconductor structure of claim 17 , wherein the substrate comprises a silicon wafer.
19. The semiconductor structure of claim 17 , wherein the gap fill dielectric layer comprises a flowable oxide.
20. The semiconductor structure of claim 19 , wherein the flowable oxide is a self-planarizing material.