Integrated circuits with spacer chamfering and methods of spacer chamfering
Semiconductor devices and methods for forming the devices with spacer chamfering. One method includes, for instance: obtaining a wafer with at least one source, at least one drain, and at least one fin; forming at least one sacrificial gate with at least one barrier layer; forming a first set of spacers adjacent to the at least one sacrificial gate; forming at least one second set of spacers adjacent to the first set of spacers; and etching to remove a portion of the first set of spacers above the at least one barrier layer to form a widened opening. An intermediate semiconductor device is also disclosed.
1. A method comprising:
obtaining a wafer with at least one source, at least one drain, and at least one fin;
forming at least one sacrificial gate with at least one barrier layer, comprising:
depositing a first polysilicon layer over the wafer;
forming the at least one barrier layer over the first polysilicon layer;
depositing a second polysilicon layer over the barrier layer; and
depositing a hard mask layer over the second polysilicon layer;
forming a first set of spacers adjacent to the at least one sacrificial gate;
forming at least one second set of spacers adjacent to the first set of spacers; and
etching to remove a portion of the first set of spacers above the at least one barrier layer to form a widened opening.
2. The method of claim 1 , wherein etching to remove a portion of the first set of spacers above the at least one barrier layer comprises:
removing the hard mask layer; and
etching to remove the second polysilicon layer down to the barrier layer.
3. The method of claim 2 , further comprising:
removing the barrier layer;
etching to remove the first polysilicon layer to form an opening between a remaining portion of the first set of spacers.
4. The method of claim 3 , further comprising:
forming at least one gate contact in the widened opening and the opening between the remaining portion of the first set of spacers.
5. A method comprising:
obtaining a wafer with at least one source, at least one drain, and at least one fin;
forming at least one sacrificial gate with at least one barrier layer;
forming a first set of spacers adjacent to the at least one sacrificial gate;
forming at least one second set of spacers adjacent to the first set of spacers;
etching to remove a portion of the first set of spacers above the at least one barrier layer to form a widened opening; and
growing an epitaxial layer between at least one of the first set of spacers and the second set of spacers.
6. The method of claim 5 , wherein the at least one second set of spacers is formed adjacent to a portion of the first set of spacers after the epitaxial layer is grown.
7. The method of claim 6 , wherein the at least one second set of spacers is formed adjacent to the first set of spacers before the epitaxial layer is grown.
8. The method of claim 5 , wherein the at least one barrier layer is positioned between a first end and a second end of the first set of spacers.
9. The method of claim 6 , wherein the at least one barrier layer is positioned at a height above a top surface of the epitaxial layer.
10. The method of claim 7 , wherein the at least one barrier layer is positioned at a height below a top surface of the epitaxial layer.
11. The method of claim 1 , wherein the first polysilicon layer is conformally deposited over the at least one fin and the barrier layer is a conformal barrier layer.
12. The method of claim 1 , wherein the first polysilicon layer is a full polysilicon deposition and the barrier layer is a planar layer formed over the first polysilicon layer.