Semiconductor structure having logic region and analog region
A method can include epitaxially growing epitaxial growth material within a logic region of a semiconductor structure. A method can include performing simultaneously with the growing epitaxial growth within an analog region of the semiconductor structure. A method can include performing epitaxial growth to form an epitaxial growth formation that defines an electrode of an analog device within an analog region of the semiconductor structure, wherein the performing includes using a first surface and a second surface as seed surfaces.
1. A method of fabricating a semiconductor structure, the method comprising:
growing epitaxial growth material to form an epitaxial growth formation that defines an active logic device within a logic region of a semiconductor structure;
performing, simultaneously with the growing, epitaxial growth to form an epitaxial growth formation that defines an analog device within an analog region of the semiconductor structure.
2. The method of claim 1 , wherein the active logic device is provided by a MOSFET.
3. The method of claim 1 , wherein the analog device is provided by a bipolar device selected from the group consisting of a pn junction, an np junction of a bipolar junction transistor (BJT).
4. The method of claim 1 , wherein the logic device is a transistor that has a channel defined by a thin silicon layer of a silicon on insulator (SOI) structure.
5. The method of claim 1 , wherein the analog device is a bipolar device that has an electrode defined by a substrate of a silicon on insulator (SOI) structure.
6. The method of claim 1 , wherein the performing is provided using opposing surfaces as seed surfaces.
7. The method of claim 1 , wherein the epitaxial growth formation within a logic region defines a source-drain of an active MOSFET, and wherein the epitaxial growth formation within an analog region defines an electrode of an analog device.
8. The method of claim 1 , wherein the performing is provided using a top and bottom surface of a layer as seed surfaces.
9. The method of claim 1 , wherein the growing is provided using a top surface of a layer as a seed surface and wherein the performing is provided using a top and bottom surface of the layer as a seed surface.
10. The method of claim 1 , wherein the growing is provided using a top surface of a layer and wherein the performing is provided using top and bottom surfaces of the layer, and further simultaneously using a surface of a second layer as a seed surface.
11. The method of claim 1 , wherein the method includes prior to the performing removing material of a thin silicon layer and a dielectric layer of a silicon on insulator (SOI) structure.
12. The method of claim 1 , wherein the method includes prior to the performing, laterally recessing material of a dielectric layer of a silicon on insulator (SOI) structure.
13. A method of fabricating a semiconductor structure, the method comprising:
performing epitaxial growth to form an epitaxial growth formation that defines an electrode of an analog device within an analog region of the semiconductor structure, wherein the performing includes using a first surface and a second surface as seed surfaces.
14. The method of claim 13 , wherein the first surface and the second surface are opposing surfaces.
15. The method of claim 13 , wherein the first surface and the second surface are provided on different layers.
16. The method of claim 13 , wherein the first surface is provided on a top surface of a layer and wherein the second surface is provided by a bottom surface of the layer.
17. The method of claim 13 , wherein the semiconductor structure is formed using a silicon on insulator (SOI) structure, and wherein the epitaxial growth formation has a top elevation higher that a top elevation of the SOI structure.
18. A semiconductor structure comprising:
a substrate;
a dielectric layer formed on the substrate;
a layer formed on the dielectric layer, wherein each of the substrate, the dielectric layer and the layer extend between a logic region and an analog region, wherein within the logic region a surface of the layer is exposed to serve as an epitaxial growth seed surface, and wherein within the analog region a surface of the layer and a surface of the substrate are exposed to serve as epitaxial growth seed surfaces.
19. The semiconductor structure of claim 18 , wherein the dielectric layer is laterally recessed in an area of the analog region where the substrate is exposed so that a bottom surface of the layer is exposed to serve an epitaxial growth seed surface.
20. The semiconductor structure of claim 18 , including an epitaxial growth formation that extends between exposed surfaces of the layer and the substrate.