Semiconductor structure including a first transistor and a second transistor

1. A semiconductor structure, comprising:

a semiconductor substrate;

a layer of electrically insulating material positioned above said semiconductor substrate;

a layer of semiconductor material positioned above said layer of electrically insulating material;

a first transistor, comprising:

a first source region, a first drain region, and a first channel region, wherein each of said first source, first drain, and first channel regions is formed in said semiconductor substrate;

a first gate insulation layer positioned above said first channel region, said first gate insulation layer comprising a first portion of said electrically insulating material; and

an electrically conductive first gate electrode positioned above said first gate insulation layer, said first gate electrode extending through a first portion of said layer of semiconductor material positioned above said first portion of said layer of electrically insulating material, wherein said first gate electrode directly contacts sidewall surfaces of said first portion of said layer of semiconductor material; and

a second transistor, comprising:

a second source region, a second drain region, and a second channel region, wherein each of said second source, second drain, and second channel regions is formed in said layer of semiconductor material;

a second gate insulation layer positioned above said second channel region; and

an electrically conductive second gate electrode positioned above said second gate insulation layer, wherein a second portion of said layer of electrically insulating material is positioned below said second channel region.

2. The semiconductor structure of claim 1 , wherein said semiconductor substrate, said layer of electrically insulating material, and said layer of semiconductor material comprise a fully depleted semiconductor-on-insulator (FDSOI) substrate.

3. The semiconductor structure of claim 1 , wherein said second transistor is a logic transistor and said first transistor is a high-voltage transistor, said first transistor being adapted for operation at a higher voltage than said second transistor.

4. The semiconductor structure of claim 1 , wherein said first transistor is an input/output transistor.

5. The semiconductor structure of claim 1 , wherein said first transistor is a laterally-diffused metal-oxide-semiconductor (LDMOS) transistor.

6. The semiconductor structure of claim 5 , wherein said first transistor further comprises a body contact region formed in said semiconductor substrate and a well region formed in said semiconductor substrate, said body contact region being positioned adjacent to said first source region, and said well region extending laterally beneath at least said first source region and said body contact region.

7. The semiconductor structure of claim 1 , further comprising a trench isolation structure that extends through said layer of semiconductor material, extends through said layer of electrically insulating material, and extends into said semiconductor substrate, said trench isolation structure electrically separating said first transistor from said second transistor.

8. The semiconductor structure of claim 1 , wherein said first gate electrode is positioned directly on said first portion of said layer of electrically insulating material.

9. The semiconductor structure of claim 1 , wherein said first gate electrode comprises at least one of doped polysilicon and a work function metal layer.

10. The semiconductor structure of claim 1 , wherein said second gate insulation layer comprises a high-k dielectric material and said second gate electrode comprises a work function metal layer.

11. The semiconductor structure of claim 1 , wherein said first portion of said layer of semiconductor material directly contacting said first gate electrode comprises an extension of said first gate electrode that is positioned adjacent to and laterally surrounds a lower portion of said first gate electrode.

12. The semiconductor structure of claim 1 , further comprising one or more sidewall spacers positioned adjacent to said first gate electrode.

13. The semiconductor structure of claim 12 , wherein a portion of said layer of semiconductor material is positioned between said one or more sidewall spacers and said first portion of said layer of electrically insulating material.

14. A semiconductor structure, comprising:

a semiconductor substrate;

a layer of electrically insulating material positioned above said semiconductor substrate;

a layer of semiconductor material positioned above said layer of electrically insulating material;

a first transistor, comprising:

a first source region, a first drain region, a first channel region, a first well region, and a body contact region, wherein each of said first source, first drain, first channel, first well, and body contact regions is formed in said semiconductor substrate, wherein said first source region is positioned adjacent to said body contact region, and wherein said first source and drain regions are doped with an opposite type of dopant to said body contact region;

a first gate insulation layer positioned above said first channel region, said first gate insulation layer comprising a first portion of said electrically insulating material; and

an electrically conductive first gate electrode positioned above said first gate insulation layer, said first gate electrode extending through a first portion of said layer of semiconductor material positioned above said first portion of said layer of electrically insulating material, wherein said first gate electrode directly contacts sidewall surfaces of said first portion of said layer of semiconductor material; and

a second transistor, comprising:

a second source region, a second drain region, and a second channel region, wherein each of said second source, second drain, and second channel regions is formed in said layer of semiconductor material;

a second gate insulation layer positioned above said second channel region; and

an electrically conductive second gate electrode positioned above said second gate insulation layer, wherein a second portion of said layer of electrically insulating material is positioned below said second channel region and on an opposite side of said layer of semiconductor material from said second gate insulation layer and said second gate electrode.

15. The semiconductor structure of claim 14 , wherein said first well region is doped with an opposite type of dopant to said first source and drain regions and extends laterally beneath said first source region and said body contact region, said first channel region being positioned in said first well region.

16. The semiconductor structure of claim 15 , wherein said first transistor further comprises a second well region formed in said semiconductor substrate, said second well region being doped with an opposite type of dopant to said first well region and extending laterally beneath said first source region, said body contact region, and said first drain region.

17. The semiconductor structure of claim 14 , wherein a portion of said layer of semiconductor material is positioned adjacent to and laterally surrounds a lower portion of said first gate electrode, said portion of said layer of semiconductor material comprising an extension of said first gate electrode.

18. The semiconductor structure of claim 14 , further comprising one or more sidewall spacers positioned adjacent to said first gate electrode.

19. The semiconductor structure of claim 18 , wherein a portion of said layer of semiconductor material is positioned between said one or more sidewall spacers and said first portion of said layer of electrically insulating material, said portion of said layer of semiconductor material comprising an extension of said first gate electrode.

20. A semiconductor structure, comprising:

a semiconductor substrate;

a layer of electrically insulating material positioned above said semiconductor substrate;

a layer of semiconductor material positioned above said layer of electrically insulating material;

a first transistor, comprising:

a first source region, a first drain region, a first channel region, a well region, and a body contact region, wherein each of said first source, first drain, first channel, well, and body contact regions is formed in said semiconductor substrate, wherein said first source region is positioned adjacent to said body contact region, wherein said first source and drain regions are doped with an opposite type of dopant to said body contact region, and wherein said well region is doped with an opposite type of dopant to said body contact region and extends laterally beneath said first source region, said body contact region, and said first drain region;

a first gate insulation layer positioned above said first channel region, said first gate insulation layer comprising a first portion of said electrically insulating material; and

an electrically conductive first gate electrode positioned above said first gate insulation layer, said first gate electrode extending through a first portion of said layer of semiconductor material positioned above said first portion of said layer of electrically insulating material, wherein said first gate electrode directly contacts sidewall surfaces of said first portion of said layer of semiconductor material; and

a second transistor, comprising:

a second source region, a second drain region, and a second channel region, wherein each of said second source, second drain, and second channel regions is formed in said layer of semiconductor material;

a second gate insulation layer positioned above said second channel region; and

an electrically conductive second gate electrode positioned above said second gate insulation layer, wherein a second portion of said layer of electrically insulating material is positioned below said second channel region and on an opposite side of said layer of semiconductor material from said second gate insulation layer and said second gate electrode.