Base profile of self-aligned bipolar transistors for power amplifier applications
According to a bipolar transistor structure having a transistor top and a transistor bottom herein, a silicon substrate located at the transistor bottom has a collector region of a first conductivity type. An epitaxial base layer of a second conductivity type overlies, relative to the transistor top and bottom, a portion of the collector region. The epitaxial base layer has a bottom surface on the silicon substrate and a top surface opposite the bottom surface. A top region, relative to the transistor top and bottom, of the epitaxial base layer comprises a concentration of germanium having atomic compositions sufficient to avoid impacting transistor parameters, and sufficient to be resistant to selective chemical etching. A silicon emitter layer of the first conductivity type overlies, relative to the transistor top and bottom, a portion of the epitaxial base layer adjacent to the top surface of the epitaxial base layer.
1. A method of forming a bipolar transistor structure comprising:
forming a collector region of a first conductivity type within a semiconductor substrate;
forming a base of a second conductivity type on a portion of said collector region;
forming an etch-stop region in a surface layer of said base, said surface layer being located opposite said semiconductor substrate;
controlling a concentration of germanium in said etch-stop region to have atomic compositions between 1% and 15% at the top of said surface layer, said concentration of germanium being sufficient to avoid impacting transistor parameters and sufficient to be resistant to selective chemical etching; and
forming an emitter of said first conductivity type on said etch-stop region of said base.
2. The method according to claim 1 , said forming said base comprising:
epitaxially growing said base directly on said collector region.
3. The method according to claim 1 , said forming said emitter comprising:
epitaxially growing said emitter directly on said base.
4. The method according to claim 1 , further comprising:
forming a trench surrounding said collector region simultaneously with forming said emitter; and
depositing an insulator within said trench.
5. The method according to claim 1 , further comprising:
forming sidewall spacers on sidewalls of said emitter.
6. The method according to claim 1 , said base comprising an intrinsic base portion and an extrinsic base portion, said method further comprising:
forming silicide pads on said emitter, said collector region, and said extrinsic base portion, and
forming electrical contacts connected to said silicide pads.
7. The method according to claim 1 , said concentration of germanium in said base varying according to a predetermined profile, said predetermined profile being, in cross-section, one of:
triangular shaped; and
trapezoidal shaped.
8. The method according to claim 1 , further comprising:
forming a silicon layer overlying said base.
9. A method comprising:
fabricating a device having a device top and a device bottom, said device comprising:
a collector of a bipolar transistor comprising an n-type doped collector disposed in an upper portion, relative to said device top and said device bottom, of a silicon (Si) substrate layer;
a base comprising p-type doped epitaxial silicon germanium (SiGe) disposed on said Si substrate layer above, relative to said device top and said device bottom, said n-type doped collector, said base contacting said Si substrate layer,
a top region of said base, relative to said device top and said device bottom, comprising a concentration of germanium (Ge) having atomic compositions between 1% and 15% at a top surface of said base, said concentration of germanium being sufficient to avoid impacting transistor parameters, and sufficient to be resistant to selective chemical etching; and
an emitter comprising an n-type doped silicon (Si) emitter contacting said base.
10. The method according to claim 9 , further comprising:
creating a trench surrounding said collector; and
depositing an insulator within said trench.
11. The method according to claim 9 , said base comprising an intrinsic base portion and an extrinsic base portion, said method further comprising:
forming silicide pads and electrical contacts connected to said emitter, said collector, and said extrinsic base portion.
12. The method according to claim 9 , said base further comprising:
a silicon layer overlying, relative to said device top and said device bottom, said top region of said base.
13. The method according to claim 9 , said concentration of germanium in said base varying according to a predetermined profile between said device top and said device bottom, said predetermined profile being, in cross-section between said device top and said device bottom, one of:
triangular shaped; and
trapezoidal shaped.
14. A method comprising:
providing a semiconductor substrate;
forming a collector region of a first conductivity type within said semiconductor substrate;
forming a base of a second conductivity type contacting a portion of said collector region;
forming an etch-stop region in a surface layer of said base, said surface layer being located opposite said semiconductor substrate;
controlling a concentration of germanium in said etch-stop region to have atomic compositions between 1% and 15% at said surface layer, said concentration of germanium being sufficient to avoid impacting transistor parameters and sufficient to be resistant to selective chemical etching; and
forming an emitter of said first conductivity type contacting said etch-stop region of said base.
15. The method according to claim 14 , said forming said base further comprising:
growing a single crystal epitaxially, directly on said collector region.
16. The method according to claim 14 , said forming said emitter further comprising:
growing a single crystal epitaxially, directly on said base.
17. The method according to claim 14 , further comprising:
creating a trench surrounding said collector; and
depositing an insulator within said trench.
18. The method according to claim 14 , said base comprising an intrinsic base portion and an extrinsic base portion, said method further comprising:
forming silicide pads attached to each of said emitter, said collector, and said extrinsic base portion; and
forming electrical contacts connected to each of said silicide pads.
19. The method according to claim 14 , said concentration of germanium in said base varying according to a predetermined profile, said predetermined profile being, in cross-section, one of:
triangular shaped; and
trapezoidal shaped.
20. The method according to claim 14 , further comprising:
forming a silicon layer overlying said etch-stop region.