Patent Assignment
Reel/Frame 037409/0869
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded: 2016-01-03
Received: 2016-01-03
Pages: 15
Assignor
INTERNATIONAL BUSINESS MACHINES CORPORATION
Executed: 2015-10-28
Assignee
GLOBALFOUNDRIES U.S. 2 LLC
2070 ROUTE 52, HOPEWELL JUNCTION, NY, 12533, UNITED STATES
Covered Applications
(100)
PLUG VIA FORMATION BY PATTERNED PLATING AND POLISHING
App. No. 14/788,945
→
BASE PROFILE OF SELF-ALIGNED BIPOLAR TRANSISTORS FOR POWER AMPLIFIER APPLICATIONS
App. No. 14/755,862
→
SWITCHABLE FILTERS AND DESIGN STRUCTURES
App. No. 14/755,522
→
PREDICTING AND ALERTING USER TO NAVIGATION OPTIONS AND PREDICTING USER INTENTIONS
App. No. 14/753,682
→
Copper Feature Design for Warpage Control of Substrates
App. No. 14/754,585
→
ANALYZING COMPUTER PROGRAMS TO IDENTIFY ERRORS
App. No. 14/754,013
→
METHOD FOR FABRICATING A CONTACT
App. No. 14/754,190
→
DETERMINING APPROPRIATENESS OF SAMPLING INTEGRATED CIRCUIT TEST DATA IN THE PRESENCE OF MANUFACTURING VARIATIONS
App. No. 14/753,771
→
GATE-ALL-AROUND NANOWIRE MOSFET AND METHOD OF FORMATION
App. No. 14/751,493
→
GATE-ALL-AROUND NANOWIRE MOSFET AND METHOD OF FORMATION
App. No. 14/751,542
→
FDSOI VOLTAGE REFERENCE
App. No. 14/751,557
→
Gate-All-Around Nanowire MOSFET and Method of Formation
App. No. 14/751,646
→
DYNAMIC AND ADAPTIVE TIMING SENSITIVITY DURING STATIC TIMING ANALYSIS USING LOOK-UP TABLE
App. No. 14/751,222
→
Gate-All-Around Nanowire MOSFET and Method of Formation
App. No. 14/751,706
→
Gate-All-Around Nanowire MOSFET and Method of Formation
App. No. 14/751,761
→
GENERATIVE LEARNING FOR REALISTIC AND GROUND RULE CLEAN HOT SPOT SYNTHESIS
App. No. 14/749,909
→
MANAGING METADATA FOR CACHING DEVICES DURING SHUTDOWN AND RESTART PROCEDURES
App. No. 14/750,971
→
INTEGRATED CIRCUIT (IC) CHIPS WITH THROUGH SILICON VIAS (TSV) AND METHOD OF FORMING THE IC
App. No. 14/749,843
→
MULTILEVEL WAVEGUIDE STRUCTURE
App. No. 14/749,907
→
PARTITIONING OF PROGRAM ANALYSES INTO SUB-ANALYSES USING DYNAMIC HINTS
App. No. 14/749,731
→
HETEROJUNCTION BIPOLAR TRANSISTOR WITH IMPROVED PERFORMANCE AND BREAKDOWN VOLTAGE
App. No. 14/749,809
→
Partitioning of Program Analyses into Sub-Analyses Using Dynamic Hints
App. No. 14/749,772
→
STRUCTURE FOR BEOL METAL LEVELS WITH MULTIPLE DIELECTRIC LAYERS FOR IMPROVED DIELECTRIC TO METAL ADHESION
App. No. 14/749,817
→
HIGH VOLTAGE FINFET STRUCTURE WITH SHAPED DRIFT REGION
App. No. 14/750,476
→
INSULATING A VIA IN A SEMICONDUCTOR SUBSTRATE
App. No. 14/749,750
→
MODELING LOCALIZED TEMPERATURE CHANGES ON AN INTEGRATED CIRCUIT CHIP USING THERMAL POTENTIAL THEORY
App. No. 14/748,595
→
HIGH PERFORMANCE HEAT SHIELDS WITH REDUCED CAPACITANCE
App. No. 14/748,355
→
SELF-ALIGNED EMITTER-BASE-COLLECTOR BIPOLAR JUNCTION TRANSISTORS WITH A SINGLE CRYSTAL RAISED EXTRINSIC BASE
App. No. 14/747,525
→
REPLACEMENT EMITTER FOR REDUCED CONTACT RESISTANCE
App. No. 14/747,604
→
ELECTRICAL FUSE WITH HIGH OFF RESISTANCE
App. No. 14/746,891
→
BIPOLAR JUNCTION TRANSISTORS WITH A BURIED DIELECTRIC REGION IN THE ACTIVE DEVICE REGION
App. No. 14/747,668
→
SHAPED TERMINALS FOR A BIPOLAR JUNCTION TRANSISTOR
App. No. 14/747,385
→
BIPOLAR JUNCTION TRANSISTORS WITH DOUBLE-TAPERED EMITTER FINGERS
App. No. 14/745,764
→
DEVICE STRUCTURES FOR A SILICON-ON-INSULATOR SUBSTRATE WITH A HIGH-RESISTANCE HANDLE WAFER
App. No. 14/745,704
→
CHIP PACKAGE WITH REDUCED TEMPERATURE VARIATION HAVING EMITTER FINGERS FORMATION ACCORDING TO THEIR PROXIMITY TO THE THERMAL PATHWAY STRUCTURE AND A METHOD FOR FORMING A SAME
App. No. 14/745,800
→
GENERATING TENSILE STRAIN IN BULK FINFET CHANNEL
App. No. 14/745,547
→
SUBLITHOGRAPHIC WIDTH FINFET EMPLOYING SOLID PHASE EPITAXY
App. No. 14/746,017
→
LATCHING CURRENT SENSING AMPLIFIER FOR MEMORY ARRAY
App. No. 14/744,800
→
NON-DESTRUCTIVE DIELECTRIC LAYER THICKNESS AND DOPANT MEASURING METHOD
App. No. 14/744,198
→
DETECTING A VOID BETWEEN A VIA AND A WIRING LINE
App. No. 14/743,208
→
INTEGRATED CIRCUIT CHIP RELIABILITY USING RELIABILITY-OPTIMIZED FAILURE MECHANISM TARGETING
App. No. 14/742,801
→
TEST STRUCTURES FOR DIELECTRIC RELIABILITY EVALUATIONS
App. No. 14/742,895
→
CAPACITIVE MEASUREMENTS OF DIVOTS IN SEMICONDUCTOR DEVICES
App. No. 14/742,917
→
INTEGRATED MICRO-PELTIER COOLING COMPONENTS IN SILICON-ON-INSULATOR (SOI) LAYERS
App. No. 14/743,030
→
INDUCTION HEATING FOR UNDERFILL REMOVAL AND CHIP REWORK
App. No. 14/741,757
→
WAFER-LEVEL CHIP-SCALE PACKAGE STRUCTURE UTILIZING CONDUCTIVE POLYMER
App. No. 14/741,802
→
Method and Structure to Reduce FET Threshold Voltage Shift Due to Oxygen Diffusion
App. No. 14/741,618
→
PRINTED TRANSISTOR AND FABRICATION METHOD
App. No. 14/741,169
→
STRUCTURE AND METHOD TO OBTAIN EOT SCALED DIELECTRIC STACKS
App. No. 14/739,627
→
STRUCTURE AND METHOD TO OBTAIN EOT SCALED DIELECTRIC STACKS
App. No. 14/739,686
→
LOW INTERFACIAL DEFECT FIELD EFFECT TRANSISTOR
App. No. 14/739,137
→
STRUCTURE AND METHOD TO OBTAIN EOT SCALED DIELECTRIC STACKS
App. No. 14/739,562
→
METHOD AND SYSTEM FOR USING A VIBRATION SIGNATURE AS AN AUTHENTICATION KEY
App. No. 14/739,262
→
STRUCTURE AND METHOD TO OBTAIN EOT SCALED DIELECTRIC STACKS
App. No. 14/739,669
→
MICROELECTRONIC STRUCTURE INCLUDING AIR GAP
App. No. 14/739,703
→
PLANNING ECONOMIC ENERGY DISPATCH IN ELECTRICAL GRID UNDER UNCERTAINTY
App. No. 14/738,355
→
FINFET HAVING AN EPITAXIALLY GROWN SEMICONDUCTOR ON THE FIN IN THE CHANNEL REGION
App. No. 14/738,336
→
METHODS AND STRUCTURES FOR ACHIEVING TARGET RESISTANCE POST CMP USING IN-SITU RESISTANCE MEASUREMENTS
App. No. 14/737,915
→
TAPE SERVO TRACK WRITE COMPENSATION
App. No. 14/738,025
→
METHOD AND PROTECTION APPARATUS FOR PROTECTING A THERMAL SENSITIVE COMPONENT IN A THERMAL PROCESS
App. No. 14/737,632
→
ALTERNATIVE THRESHOLD VOLTAGE SCHEME VIA DIRECT METAL GATE PATTERNING FOR HIGH PERFORMANCE CMOS FinFETs
App. No. 14/738,288
→
STRUCTURE AND METHOD OF FORMING ENHANCED ARRAY DEVICE ISOLATION FOR IMPLANTED PLATE EDRAM
App. No. 14/736,695
→
TRANSFERABLE TRANSPARENT CONDUCTIVE OXIDE
App. No. 14/736,942
→
SELECTIVE ETCH CHEMISTRY FOR GATE ELECTRODE MATERIALS
App. No. 14/736,698
→
STRUCTURE AND METHOD OF FORMING ENHANCED ARRAY DEVICE ISOLATION FOR IMPLANTED PLATE EDRAM
App. No. 14/736,651
→
BULK SEMICONDUCTOR FINS WITH SELF-ALIGNED SHALLOW TRENCH ISOLATION STRUCTURES
App. No. 14/735,466
→
COMPOSITE VIEWS FOR IP BLOCKS IN ASIC DESIGNS
App. No. 14/734,411
→
NANOPOROUS STRUCTURES BY REACTIVE ION ETCHING
App. No. 14/734,018
→
TCAM STRUCTURES WITH REDUCED POWER SUPPLY NOISE
App. No. 14/734,504
→
CIRCUIT TO IMPROVE SRAM STABILITY
App. No. 14/734,525
→
INTEGRATED CIRCUIT STRUCTURE WITH BULK SILICON FINFET
App. No. 14/734,310
→
BIPOLAR JUNCTION TRANSISTORS WITH REDUCED BASE-COLLECTOR JUNCTION CAPACITANCE
App. No. 14/734,713
→
PASSIVATION LAYER TOPOGRAPHY
App. No. 14/734,600
→
CMOS PROTECTION DURING GERMANIUM PHOTODETECTOR PROCESSING
App. No. 14/732,835
→
THRU-SILICON-VIA STRUCTURES
App. No. 14/733,445
→
INTERCONNECT STRUCTURE AND METHOD FOR FABRICATING ON-CHIP INTERCONNECT STRUCTURES BY IMAGE REVERSAL
App. No. 14/733,652
→
SLURRY FOR CHEMICAL-MECHANICAL POLISHING OF METALS AND USE THEREOF
App. No. 14/733,235
→
BREAKDOWN VOLTAGE MULTIPLYING INTEGRATION SCHEME
App. No. 14/732,680
→
FLEXIBLE, STRETCHABLE ELECTRONIC DEVICES
App. No. 14/732,689
→
BONDED EPITAXIAL OXIDE STRUCTURES FOR COMPOUND SEMICONDUCTOR ON SILICON SUBSTRATES
App. No. 14/732,705
→
GATE STRUCTURES WITH PROTECTED END SURFACES TO ELIMINATE OR REDUCE UNWANTED EPI MATERIAL GROWTH
App. No. 14/731,569
→
SILICON GERMANIUM FIN
App. No. 14/730,320
→
Laser Surgical Apparatus and Methods of its Use Minimizing Damage During the Ablation of Tissue Using a Focused Ultrashort Pulsed Laser Beam Wherein the Slope of Fluence Breakdown is a Function of the Pulse Width
App. No. 14/730,503
→
Automating Capacity Upgrade on Demand
App. No. 14/730,375
→
METHOD AND STRUCTURE FOR DETERMINING THERMAL CYCLE RELIABILITY
App. No. 14/729,446
→
Automatic Analytical Cloud Scaling of Hardware Using Resource Sub-Cloud
App. No. 14/729,177
→
METHOD AND STRUCTURE TO FORM TENSILE STRAINED SIGE FINS AND COMPRESSIVE STRAINED SIGE FINS ON A SAME SUBSTRATE
App. No. 14/729,845
→
CONTACTS TO SEMICONDUCTOR SUBSTRATE AND METHODS OF FORMING SAME
App. No. 14/729,298
→
DESIGN OF TEMPERATURE-COMPLIANT INTEGRATED CIRCUITS
App. No. 14/728,100
→
VIRTUAL MACHINE BACKUP
App. No. 14/727,245
→
MERGED SOURCE DRAIN EPITAXY
App. No. 14/727,219
→
SUB-NANOSECOND DISTRIBUTED CLOCK SYNCHRONIZATION USING ALIGNMENT MARKER IN ETHERNET IEEE 1588 PROTOCOL
App. No. 14/726,945
→
HETEROJUNCTION BIPOLAR TRANSISTORS WITH INTRINSIC INTERLAYERS
App. No. 14/725,755
→
HETEROJUNCTION BIPOLAR TRANSISTORS WITH INTRINSIC INTERLAYERS
App. No. 14/725,795
→
SELECTIVE GALLIUM NITRIDE REGROWTH ON (100) SILICON
App. No. 14/725,581
→
PASSIVATION OF BACK-ILLUMINATED IMAGE SENSOR
App. No. 14/725,151
→
VACUUM TRAP
App. No. 14/723,703
→
FINFET SEMICONDUCTOR DEVICE HAVING INCREASED GATE HEIGHT CONTROL
App. No. 14/723,681
→
METHODS TO FORM CONDUCTIVE THIN FILM STRUCTURES
App. No. 14/722,302
→
DOPING OF COPPER WIRING STRUCTURES IN BACK END OF LINE PROCESSING
App. No. 14/722,411
→