Generating tensile strain in bulk finFET channel
View Patent ↗Embodiments of the present invention provide a method of forming fin-type transistors. The method includes forming a finFET structure having a fin channel region underneath a gate structure, and a source region and a drain region directly adjacent to the fin channel region at two opposing sides of the gate structure; and subjecting the source region and the drain region to a compressive strain; thereby causing the source region and the drain region to exert a tensile strain to the fin channel region. A finFET transistor formed thereby is also provided, which includes a channel region of fin shape covered by a gate on top thereof; a source next to a first end of the channel region on a first side of the gate; and a drain next to a second end of the channel region on a second side of the gate, wherein the source and drain are made of epitaxially grown silicon-germanium (SiGe) having a Ge concentration level of at least 50% atomic percentage covered with silicon cap.
1. A method comprising:
forming a finFET structure having a fin channel region underneath a gate structure, and a source region and a drain region directly adjacent to said fin channel region at two opposing sides of said gate structure, wherein forming said finFET structure includes:
covering a fin on a substrate with said gate structure;
forming sidewall spacers adjacent to sidewalls of said gate structure; and
forming said fin channel region by removing portions of said fin that are not covered by said gate structure and said sidewall spacers; and
subjecting said source region and said drain region to a compressive stress; thereby causing said source region and said drain region to exert a tensile stress to said fin channel region.
2. The method of claim 1 , wherein forming said finFET structure comprises epitaxially growing fully relaxed silicon-germanium (SiGe) at said two opposing sides of said fin channel region to form said source region and said drain region, wherein said SiGe of said source region and said drain region has a Ge concentration level of at least 50% in atomic percentage.
3. The method of claim 2 , wherein epitaxially growing said fully relaxed SiGe comprises forming said source region and said drain region by growing said SiGe to have stacking faults and dislocations, and using said Ge concentration level to control amount of said stacking faults and dislocations inside said source region and said drain region.
4. The method of claim 1 , wherein subjecting said source region and said drain region to said compressive stress comprises epitaxially growing a silicon cap layer on top of and covering said source region and said drain region, wherein said silicon cap layer has a lattice constant that is smaller than that of said source region and said drain region.
5. The method of claim 4 , wherein said silicon cap layer has a thickness ranging from about 5 nm to about 30 nm, causing said source region and said drain region to exert a tensile stress to and result in a tensile strain of at least 0.7% in said fin channel region.
6. The method of claim 4 , wherein growing said silicon cap layer covering said source region and said drain region causes said source region and said drain region to become a stressed source and drain with a compressive strain of at least −1.8%.
7. A method comprising:
providing a semiconductor substrate with one or more fins on top thereof;
covering a lower portion of said one or more fins in an insulating material;
covering a fin channel region of said one or more fins using a gate structure;
forming sidewall spacers next to two opposing sidewalls of said gate structure;
removing portions of said one or more fins that are not covered by said gate structure and not covered by said sidewall spacers, thereby exposing cross-sections of said one or more fins at surfaces of said sidewall spacers and said insulating material;
epitaxially growing silicon-germanium (SiGe) from said exposed cross-sections of said one or more fins to form a source region and a drain region directly adjacent to said fin channel region at two opposing sides of said gate structure; and
subjecting said source region and said drain region to a compressive stress; thereby causing said source region and said drain region to exert a tensile stress to said fin channel region.
8. The method of claim 7 , wherein epitaxially growing said SiGe comprises forming said source region and said drain region by said SiGe to have stacking faults and dislocations, and using a Ge concentration level in said SiGe of at least 50% in atomic percentage to control amount of said stacking faults and dislocations inside said source region and said drain region.
9. The method of claim 7 , wherein subjecting said source region and said drain region to said compressive stress comprises epitaxially growing a silicon cap layer on top of and covering said source region and said drain region, wherein said silicon cap layer, during a course of formation thereof, applies said compressive stress towards said source region and said drain region of which said silicon cap layer encompasses.
10. The method of claim 9 , wherein said silicon cap layer has a thickness ranging from about 5 nm to about 30 nm, said thickness being sufficient to cause said source region and said drain region to be pulled in a direction away from said fin channel region thereby resulting in a tensile strain of at least 0.7% inside said fin channel region.
11. The method of claim 9 , wherein growing said silicon cap layer covering said source region and said drain region causes said source region and said drain region to become stressed source and drain of a finFET with a compressive strain of at least −1.8%.