STRUCTURE AND METHOD OF FORMING ENHANCED ARRAY DEVICE ISOLATION FOR IMPLANTED PLATE EDRAM
A memory device is provided including a semiconductor on insulator (SOI) substrate including a first semiconductor layer atop a buried dielectric layer, wherein the buried dielectric layer is overlying a second semiconductor layer. A capacitor is present in a trench, wherein the trench extends from an upper surface of the first semiconductor layer through the buried dielectric layer and extends into the second semiconductor layer. A protective oxide is present in a void that lies adjacent the first semiconductor layer, and a pass transistor is present atop the semiconductor on insulator substrate in electrical communication with the capacitor.
1 . A memory device comprising:
a semiconductor on insulator (SOI) substrate including, from top to bottom, a first semiconductor layer, a buried dielectric layer, and a second semiconductor layer; wherein an entirety of said buried dielectric layer is positioned between a bottommost surface of said first semiconductor layer and a topmost surface of said second semiconductor layer;
a capacitor present in a trench, wherein said trench extends from an upper surface of said first semiconductor layer through said buried dielectric layer and extends into said second semiconductor layer;
a protective oxide present in a void that lies adjacent said first semiconductor layer, wherein said protective oxide layer has an outer vertical edge that forms an upper sidewall surface of said trench and has a bottommost surface that contacts a topmost surface of said buried dielectric layer and a width that is less than a width of said buried dielectric layer; and
a pass transistor present atop said semiconductor on insulator substrate and in electrical communication with said capacitor.
2 . The memory device of claim 1 , wherein said void has a width from 2 nm to 10 nm.
3 . The memory device of claim 1 , wherein a width of said trench within said second semiconductor layer is greater than a width of said trench located above said second semiconductor layer.
4 . The memory device of claim 1 , wherein said outer vertical edge of said protective oxide is vertically coincident to an edge of said buried dielectric layer.
5 . The memory device of claim 1 , wherein said first semiconductor layer has a vertical edge that is laterally offset from a vertical edge of said buried dielectric layer.
6 . The memory device of claim 1 , wherein said protective oxide is a thermal oxide.
7 . The memory device of claim 1 , wherein said protective oxide entirely fills said void.
8 . The memory device of claim 1 , wherein said protective oxide partially fills said void.
9 . The memory device of claim 1 , wherein said protective oxide is present only on one side of said trench.
10 . The memory device of claim 9 , wherein a doped polysilicon region is present on another side of said trench.
11 . The memory device of claim 10 , wherein a top trench oxide is positioned between said protective oxide and said doped polysilicon region.
12 . The memory device of claim 1 , wherein said width of said that is greater than its height.