Structure and method of forming enhanced array device isolation for implanted plate EDRAM

1. A memory device comprising:

a semiconductor on insulator (SOI) substrate including, from top to bottom, a first semiconductor layer, a buried dielectric layer, and a second semiconductor layer; wherein said first semiconductor layer has a recessed vertical edge relative to at least a vertical edge of said buried dielectric layer;

a protective oxide positioned adjacent said recessed vertical edge of said first semiconductor layer, wherein said protective oxide is present only on one side of said trench;

a capacitor present in a trench, wherein said trench extends from an upper surface of said SOI substrate through said buried dielectric layer and extends into said second semiconductor layer, and

a pass transistor in electrical communication with said capacitor and on a portion of said first semiconductor layer that is present on another side of said trench that is opposite said one side of said trench containing said protective oxide.

2. The memory device of claim 1 , further comprising a doped polysilicon region present on said another side of said trench.

3. The memory device of claim 2 , wherein an isolation region is positioned between said protective oxide and said doped polysilicon region.

4. The memory device of claim 3 , wherein said isolation region comprises a top trench oxide.

5. The memory device of claim 1 , wherein a width of said trench within said second semiconductor layer is greater than a width of said trench located above said second semiconductor layer.

6. The memory device of claim 1 , wherein said protective oxide has an outer vertical edge that is vertically coincident to an edge of said buried dielectric layer.

7. The memory device of claim 1 , wherein said protective oxide is a thermal oxide.

8. The memory device of claim 1 , wherein a first portion of said buried dielectric layer is located on said another side of said trench, and said first portion of said buried oxide extends beneath the pass transistor and overlaps a portion of said capacitor.

9. The memory device of claim 8 , wherein a second portion of said buried dielectric layer is located on said one side of said trench containing said protective oxide, and wherein a bottommost surface of said protective oxide is located on a topmost surface of said second portion of said buried dielectric layer.

10. The memory device of claim 9 , wherein a topmost surface of said second portion of said buried dielectric layer is coplanar with a topmost surface of said first portion of said buried dielectric layer, and wherein a bottommost surface of said second portion of said buried dielectric layer is coplanar with a bottommost of said first portion of said buried dielectric layer.

11. The memory device of claim 9 , wherein a width of said protective oxide is less than a width of said second portion of said buried dielectric layer.

12. The memory device of claim 1 , wherein said capacitor comprises a bottom electrode, a node dielectric and an upper electrode, wherein a topmost surface of said upper electrode is located between a topmost and a bottommost surface of said buried dielectric layer.

13. The memory device of claim 1 , wherein said protective oxide has a topmost surface that is coplanar with a topmost surface of said first semiconductor material layer.

14. The memory device of claim 1 , wherein said first semiconductor layer containing said recessed edge and said protective oxide does not extend beneath said pass transistor.

15. The memory device of claim 1 , wherein an entirety of said buried dielectric layer is located between a bottommost surface of said first semiconductor layer and a topmost surface of said second semiconductor layer.