High performance heat shields with reduced capacitance
View Patent ↗Methods and structures for capacitively isolating a heat shield from a handle wafer of a silicon-on-insulator substrate. A contact plug is located in a trench extending through a trench isolation region in a device layer of the silicon-on-insulator substrate and at least partially through a buried insulator layer of the silicon-on-insulator substrate. The heat shield is located in an interconnect structure, which also includes a wire coupling the heat shield with the contact plug. An isolation structure is positioned between the contact plug and a portion of the handle wafer. The isolation structure provides the capacitive isolation.
1. A structure formed using a silicon-on-insulator substrate that includes a device layer, a buried insulator layer, and a handle wafer, the structure comprising:
a trench isolation region in the device layer;
a contact plug in a trench extending through the trench isolation region and at least only partially through the buried insulator layer;
an interconnect structure including a heat shield and a first wire coupling the heat shield with the contact plug; and
an isolation structure between the contact plug and a portion of the handle wafer,
wherein the isolation structure capacitively isolates the heat shield from the handle wafer, and the isolation structure comprises a portion of the buried insulator layer between the contact plug and the handle wafer.
2. The structure of claim 1 wherein the isolation structure comprises a junction capacitor.
3. The structure of claim 1 wherein the isolation structure provides a first capacitance and the heat shield provides a second capacitance coupled by the first wire with the isolation structure in order to reduce the second capacitance of the heat shield.
4. The structure of claim 1 wherein the interconnect structure includes a second wire and the device layer includes a device structure capable of generating heat when powered, and the heat shield is located between the device structure and the second wire.
5. The structure of claim 1 wherein the heat shield is formed in a first metallization level of the interconnect structure, and the device structure is a passive device located in a second level of the interconnect structure between the first metallization level and the device layer.
6. A structure formed using a silicon-on-insulator substrate that includes a device layer, a buried insulator layer, and a handle wafer, the structure comprising:
a trench isolation region in the device layer;
a contact plug in a trench extending through the trench isolation region and through the buried insulator layer to the handle wafer;
an interconnect structure including a heat shield and a first wire coupling the heat shield with the contact plug; and
an isolation structure between the contact plug and a portion of the handle wafer,
wherein the isolation structure capacitively isolates the heat shield from the handle wafer, the isolation structure comprises a doped region in a portion of the handle wafer adjacent to a bottom surface of the trench, the doped region has a first conductivity type, and the portion of the handle wafer has a second conductivity type opposite from the first conductivity type.
7. The structure of claim 6 wherein the isolation structure comprises a junction capacitor.
8. The structure of claim 6 wherein the isolation structure provides a first capacitance and the heat shield provides a second capacitance coupled by the first wire with the isolation structure in order to reduce the second capacitance of the heat shield.
9. The structure of claim 6 wherein the interconnect structure includes a second wire and the device layer includes a device structure capable of generating heat when powered, and the heat shield is located between the device structure and the second wire.
10. The structure of claim 6 wherein the heat shield is formed in a first metallization level of the interconnect structure, and the device structure is a passive device located in a second level of the interconnect structure between the first metallization level and the device layer.
11. A structure formed using a silicon-on-insulator substrate that includes a device layer, a buried insulator layer, and a handle wafer, the structure comprising:
a trench isolation region in the device layer;
a contact plug in a trench extending through the trench isolation region and at least partially through the buried insulator layer;
an interconnect structure including a heat shield and a first wire coupling the heat shield with the contact plug; and
an isolation structure between the contact plug and a portion of the handle wafer,
wherein the isolation structure capacitively isolates the heat shield from the handle wafer, the handle wafer includes a bulk wafer and an epitaxial layer of opposite conductivity type from the bulk wafer, and the isolation structure includes a deep trench moat that extends through the trench isolation region in the device layer, through the buried insulator layer, and through the epitaxial layer into the bulk wafer, and the isolation structure comprises a portion of the epitaxial layer surrounded by the deep trench moat.
12. The structure of claim 11 wherein the isolation structure comprises a deep trench moat capacitor.
13. The structure of claim 11 wherein the isolation structure provides a first capacitance and the heat shield provides a second capacitance coupled by the first wire with the isolation structure in order to reduce the second capacitance of the heat shield.
14. The structure of claim 11 wherein the interconnect structure includes a second wire and the device layer includes a device structure capable of generating heat when powered, and the heat shield is located between the device structure and the second wire.
15. The structure of claim 11 wherein the heat shield is formed in a first metallization level of the interconnect structure, and the device structure is a passive device located in a second level of the interconnect structure between the first metallization level and the device layer.