Sub-nanosecond distributed clock synchronization using alignment marker in ethernet IEEE 1588 protocol

1. A method for determining a slave clock to master clock time difference with an alignment marker, the method comprising:

receiving, by a processor, a first message that was sent at a first time and that includes a first alignment marker, wherein the processor has a slave clock, wherein the first alignment marker was selected by a computing device that has a master clock;

recording, by the processor, a second time that the first message was received;

receiving, by the processor, a second message that indicates the first time at which the first message was sent and an identity of the first alignment marker, wherein the second message was transmitted subsequent to the first message being transmitted;

identifying, by the processor, the first alignment marker in a receiver based, at least in part, on the identity of the first alignment marker;

determining, by the processor, a delay that is associated with data transmission between the receiver and a transmitter, the delay being determined based on information acquired during transmission of messages between the processor and the computing device; and

generating, by the processor, a time difference from the slave clock to the master clock based, at least in part, on the delay, the first time, and the second time.

2. The method of claim 1 , wherein the determining of the delay is comprised of:

selecting, by the processor, a second alignment marker;

transmitting, by the processor, at a third time, the second alignment marker as part of a third message to the computing device;

subsequent to transmitting the third message, transmitting, by the processor, a fourth message to the computing device that contains an identity of the second alignment marker;

receiving, by the processor, a fifth message that indicates a fourth time at which the third message was received by the computing device and the identity of the second alignment marker; and

computing, by the processor, the delay using the third time and the fourth time.

3. The method of claim 2 , wherein the time difference from the slave clock to the master clock is calculated as (t 4 +t 1 −t 3 −t 2 )/2, where t 1 is the first time, t 2 is the second time, t 3 is the third time, and t 4 is the fourth time.

4. The method of claim 1 , wherein the first alignment marker is in virtual lane 0 .

5. The method of claim 2 , wherein the first alignment marker and the second alignment marker are in virtual lane 0 .

6. The method of claim 1 , wherein the second message is a sync message.

7. The method of claim 2 , wherein the second message, the fourth message, and the fifth message are sync messages.

8. A computer program product for determining a slave clock to master clock time difference with an alignment marker, the computer program product comprising:

one or more computer readable storage media and program instructions stored on the one or more computer readable storage media and executable by a processor, the program instructions comprising:

program instructions to receive a first message that was sent at a first time and that includes a first alignment marker, wherein the processor has a slave clock, wherein the first alignment marker was selected by a computing device that has a master clock;

program instructions to record a second time that the first message was received;

program instructions to receive a second message that indicates the first time at which the first message was sent and an identity of the first alignment marker, wherein the second message was transmitted subsequent to the first message being transmitted;

program instructions to identify the first alignment marker in a receiver based, at least in part, on the identity of the first alignment marker;

program instructions to determine a delay in the receiver that is associated with data transmission between the receiver and a transmitter, the delay being determined based on information acquired during transmission of messages between the processor and the computing device; and

program instructions to generate a time difference from the slave clock to the master clock based, at least in part, on the delay, the first time, and the second time.

9. The computer program product of claim 8 , wherein the program instructions to determine the delay are comprised of:

program instructions to select a second alignment marker;

program instructions to transmit at a third time, the second alignment marker as part of a third message to the computing device;

program instructions to, subsequent to transmitting the third message, transmitting, a fourth message to the computing device that contains an identity of the second alignment marker;

program instructions to receive a fifth message that indicates a fourth time at which the third message was received by the computing device and the identity of the second alignment marker; and

program instructions to compute the delay using the third time and the fourth time.

10. The computer program product of claim 9 , wherein program instructions calculate the time difference from the slave clock to the master clock as (t 4 +t 1 −t 3 −t 2 )/2, where t 1 is the first time, t 2 is the second time, t 3 is the third time, and t 4 is the fourth time.

11. The computer program product of claim 8 , wherein the first alignment marker is in virtual lane 0 .

12. The computer program product of claim 9 , wherein the first alignment marker and the second alignment marker are in virtual lane 0 .

13. The computer program product of claim 8 , wherein the second message is a sync message.

14. The computer program product of claim 9 , wherein the second message, the fourth message, and the fifth message are sync messages.

15. A computer system for determining a slave clock to master clock time difference with an alignment marker, the computer system comprising:

one or more computer processors, one or more computer readable storage media, and program instructions stored on the computer readable storage media for execution by a processor of the one or more processors, the program instructions comprising:

program instructions to receive a first message that was sent at a first time and that includes a first alignment marker, wherein the processor has a slave clock, wherein the first alignment marker was selected by a computing device that has a master clock;

program instructions to record a second time that the first message is received;

program instructions to receive a second message that indicates the first time at which the first message was sent and an identity of the first alignment marker, wherein the second message was transmitted subsequent to the first message being transmitted;

program instructions to identify the first alignment marker in a receiver based, at least in part, on the identity of the first alignment marker;

program instructions to determine a delay that is associated with data transmission between the receiver and a transmitter, the delay being determined based on information acquired during transmission of messages between the processor and the computing device; and

program instructions to generate a time difference from the slave clock to the master clock based, at least in part, on the delay, the first time, and the second time.

16. The computer system of claim 15 , wherein the program instructions to determine the delay are comprised of:

program instructions to select a second alignment marker;

program instructions to transmit at a third time, the second alignment marker as part of a third message to the computing device;

program instructions to, subsequent to transmitting the third message, transmitting, a fourth message to the computing device that contains an identity of the second alignment marker;

program instructions to receive a fifth message that indicates a fourth time at which the third message was received by the computing device and the identity of the second alignment marker; and

program instructions to compute the delay using the third time and the fourth time.

17. The computer system of claim 16 , wherein program instructions calculate the time difference from the slave clock to the master clock as (t 4 +t 1 −t 3 −t 2 )/2, where t 1 is the first time, t 2 is the second time, t 3 is the third time, and t 4 is the fourth time.

18. The computer system of claim 15 , wherein the first alignment marker is in virtual lane 0 .

19. The computer system of claim 16 wherein the first alignment marker and the second alignment marker are in virtual lane 0 .

20. The computer system of claim 15 , wherein the second message is a sync message.