FDSOI voltage reference

1. A reference device, comprising:

a fully depleted n-type metal oxide-silicon field effect transistor (MOSFET) implemented as a long channel device having a substantially undoped body; and

a fully depleted p-type MOSFET implemented with as a long channel device having a substantially undoped body;

wherein the n-type MOSFET and p-type MOSFET are connected in series and employ identical gate stacks, wherein each MOSFET has a gate electrically coupled to a respective drain thereof to form two diodes, and wherein both diodes are in one of an on state and an off state according to a polarity of an electrical potential applied across the n-type MOSFET and p-type MOSFET.

2. The reference device of claim 1 , wherein the n-type MOSFET and p-type MOSFET include FinFETs.

3. The reference device of claim 1 , wherein the n-type MOSFET and p-type MOSFET include fully depleted semiconductor-on-insulator (FDSOI) planar MOSFETs.

4. The reference device of claim 1 , wherein a source of the n-type MOSFET provides a negative terminal, a source of the p-type MOSFET provides a positive terminal, and gates of both the n-type MOSFET and p-type MOSFET are connected to a drain of both the n-type MOSFET and p-type MOSFET.

5. The reference device of claim 1 , wherein a drain of the n-type MOSFET provides a positive terminal, a drain of the p-type MOSFET provides a negative terminal, the gate of the n-type MOSFET is connected to the drain of the n-type MOSFET, the gate of the p-type MOSFET is connected to the drain of the p-type MOSFET, and a source of both the n-type MOSFET and p-type MOSFET are connected.

6. The reference device of claim 1 , wherein an output reference voltage is less than one volt.

7. The reference device of claim 6 , where the output reference voltage is approximately 0.7 volts.

8. An integrated circuit (IC) having a reference device, comprising:

a fully depleted n-type metal oxide-silicon field effect transistor (MOSFET) implemented as a long channel device having a substantially undoped body; and

a fully depleted p-type MOSFET implemented as a long channel device having a substantially undoped body;

wherein the n-type MOSFET and p-type MOSFET are connected in series and employ identical gate stacks, wherein each has a gate electrically coupled to a drain thereof, and both are in one of an on state and an off state according to a polarity of an electrical potential applied across the n-type MOSFET and p-type MOSFET.

9. The IC of claim 8 , wherein the reference device operates with a reference output voltage less than one volt.

10. The IC of claim 8 , wherein the n-type MOSFET and p-type MOSFET include FinFETs.

11. The IC of claim 8 , wherein the n-type MOSFET and p-type MOSFET include fully depleted semiconductor-on-insulator (FDSOI) planar MOSFETs.

12. The IC of claim 8 , wherein a source of the n-type MOSFET provides a negative terminal, a source of the p-type MOSFET provides a positive terminal, and gates of both the n-type MOSFET and p-type MOSFET are connected to a drain of both the n-type MOSFET and p-type MOSFET.

13. The IC of claim 8 , wherein a drain of the n-type MOSFET provides a positive terminal, a drain of the p-type MOSFET provides a negative terminal, a gate of the n-type MOSFET is connected to the drain of the n-type MOSFET, a gate of the p-type MOSFET is connected to the drain of the p-type MOSFET, and a source of both the n-type MOSFET and p-type MOSFET are connected.

14. A method of forming a reference circuit, comprising:

forming a fully depleted n-type metal oxide-silicon field effect transistor (MOSFET) and a fully depleted p-type MOSFET adjacent each other, wherein both MOSFETs are implemented as long channel devices having substantially undoped bodies, and wherein each has a commonly formed gate stack; and

wiring the n-type MOSFET and p-type MOSFET in series in which each has a gate electrically coupled to a drain thereof and both can be placed in one of an on state and an off state according to a polarity of an electrical potential applied across the n-type MOSFET and p-type MOSFET.

15. The method of claim 14 , wherein the forming includes forming the n-type MOSFET and p-type MOSFET as FinFET structures.

16. The method of claim 14 , wherein the forming includes forming the n-type MOSFET and p-type MOSFET as fully depleted semiconductor-on-insulator (FDSOI) planar MOSFETs.

17. The method of claim 14 , wherein a source of the n-type MOSFET is arranged to provide a negative terminal, a source of the p-type MOSFET is arranged to provide a positive terminal, and gates of both the n-type MOSFET and p-type MOSFET are connected to a drain of both the n-type MOSFET and p-type MOSFET.

18. The method of claim 17 , wherein gates of both the n-type MOSFET and p-type MOSFET and drains of both the n-type MOSFET and p-type MOSFET are connected with vias and a via strap.

19. The method of claim 14 , wherein a drain of the n-type MOSFET is arranged to provide a positive terminal, a drain of the p-type MOSFET is arranged to provide a negative terminal, and wherein the gate of the n-type MOSFET is connected to the drain of the n-type MOSFET, the gate of the p-type MOSFET is connected to the drain of the p-type MOSFET, and a source of both the n-type MOSFET and p-type MOSFET are connected.

20. The method of claim 19 , wherein the gate of the n-type MOSFET is connected to the drain of the n-type MOSFET with vias and a wire, the gate of the p-type MOSFET is connected to the drain of the p-type MOSFET with vias and a wire, and the source of both the n-type MOSFET and p-type MOSFET are connected with vias and a wire.