Gate-all-around nanowire MOSFET and method of formation
View Patent ↗A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a portion of the nanowire and a portion of the insulator layer; forming recesses in the insulator layer on opposing sides of the dummy gate; forming spacers on opposing sides of the dummy gate; forming source regions and drain regions in the recesses in the insulator layer on opposing sides of the dummy gate; depositing an interlayer dielectric on the source regions and the drain regions; removing the dummy gate to form a trench; removing the insulator layer under the nanowire such that a width of the trench underneath the nanowire is equal to or less than a distance between the spacers; and forming a replacement gate in the trench.
1. A gate-all-around structure for a semiconductor device, comprising:
a substrate;
an insulator layer disposed on the substrate;
a nanowire substantially laterally disposed on the insulator layer;
a source region disposed in communication with a first end of the nanowire;
a drain region disposed in communication with a second end of the nanowire;
a gate positioned substantially transverse to the nanowire, a bottom portion of the gate surrounds a portion of the nanowire between the source region and the drain region, and wherein the width of the bottom portion of the gate is less than the width of a top portion of the gate; and
a layer of high-k dielectric material disposed on the nanowire between the gate and the nanowire;
wherein the substrate and the insulator layer define a silicon-on-insulator wafer.
2. The structure of claim 1 , further comprising spacers positioned on opposing sides of the gate.
3. The structure of claim 2 , wherein inner facing surfaces on lower portions of the spacers extend laterally inward.
4. The structure of claim 3 , wherein outward facing surfaces on lower portions of the spacers extend laterally outward underneath the nanowires.
5. The structure of claim 2 , wherein the spacers comprise SiO 2 , silicon nitride, SiO x N y , or boron nitride.
6. The structure of claim 1 , wherein the gate is a replacement metal gate.
7. The structure of claim 1 , wherein the gate comprises a gate metal disposed on the layer of high-k dielectric material.
8. The structure of claim 7 , wherein the gate metal comprises aluminum, nickel, tantalum, tantalum nitride, titanium, titanium nitride, TiAl alloy, ruthenium, or tungsten.
9. The structure of claim 1 , wherein the high-k dielectric material is tantalum oxide, zirconium oxide, aluminum oxide, SiO 2 , or Al 3 N 4 .
10. The structure of claim 1 , wherein the substrate comprises silicon carbide, a silicon alloy, germanium, germanium alloy, alloy of silicon and germanium, gallium arsenide, indium arsenide, or indium phosphide.
11. The structure of claim 1 , wherein the insulator layer comprises silicon dioxide.
12. The structure of claim 1 , further comprising an interlayer dielectric material disposed on the source region and the drain region.
13. A gate-all-around structure for a semiconductor device, comprising:
a substrate having an insulator layer disposed thereon, the substrate and the insulator layer defining a silicon-on-insulator wafer;
a nanowire substantially laterally disposed on the insulator layer;
a source region disposed in communication with a first end of the nanowire;
a drain region disposed in communication with a second end of the nanowire;
a layer of high-k dielectric material disposed on the nanowire; and
a gate positioned substantially transverse to the nanowire and on the layer of high-k dielectric material and spacers positioned on opposing sides of the gate, and a bottom portion of the gate surrounds a portion of the nanowire between the source region and the drain region, wherein the bottom portion of the gate under the nanowire is narrower than a top portion of the gate above the nanowire.
14. The structure of claim 13 , wherein inner facing surfaces at bottom portions of the spacers extend inward into the gate.
15. The structure of claim 14 , wherein outward facing surfaces at bottom portions of the spacers extend outward underneath the nanowires.
16. The structure of claim 13 , wherein the high-k dielectric material disposed on the nanowire is tantalum oxide, zirconium oxide, aluminum oxide, SiO 2 , or Al 3 N 4 .
17. The structure of claim 13 , wherein the gate comprises aluminum, nickel, tantalum, tantalum nitride, titanium, titanium nitride, TiAl alloy, ruthenium, or tungsten.
18. The structure of claim 13 , wherein the insulator layer is a buried oxide layer.
19. The structure of claim 13 , further comprising an interlayer dielectric material disposed on the source region and the drain region.