Bulk semiconductor fins with self-aligned shallow trench isolation structures
A silicon-carbon alloy layer and a silicon-germanium alloy layer are sequentially formed on a silicon-containing substrate with epitaxial alignment. Trenches are formed in the silicon-germanium alloy layer by an anisotropic etch employing a patterned hard mask layer as an etch mask and the silicon-carbon alloy layer as an etch stop layer. Fin-containing semiconductor material portions are formed on a bottom surface and sidewalls of each trench with epitaxial alignment with the silicon-germanium alloy layer and the silicon-carbon alloy layer. The hard mask layer and the silicon-germanium alloy layer are removed, and an oxygen-impermeable spacer is formed on sidewalls of each fin-containing semiconductor material portion. Physically exposed semiconductor portions are converted into semiconductor oxide portions, and the oxygen-impermeable spacers are removed. The remaining portions of the fin-containing semiconductor portions include semiconductor fins, which can be employed to form semiconductor devices.
1. A method of forming a semiconductor structure comprising:
forming a stack, from bottom to top, of a single crystalline silicon-carbon alloy layer, a single crystalline silicon-germanium alloy layer and a hard mask layer over a substrate, wherein said single crystalline silicon-germanium alloy layer is formed on said silicon-carbon alloy layer with epitaxial alignment;
forming a trench within said single crystalline silicon-germanium alloy layer;
forming a silicon-containing material portion by selectively depositing a silicon-containing semiconductor material on sidewall surfaces of said single crystalline silicon-germanium alloy layer within said trench; and
removing said hard mask layer and said single-crystalline silicon-germanium alloy layer selective to said silicon-containing material portion, wherein said silicon-containing material portion includes at least one semiconductor fin.
2. The method of claim 1 , wherein a top surface of said single crystalline silicon-carbon alloy layer is physically exposed at a bottom of said trench.
3. The method of claim 2 , further comprising forming a shallow trench isolation structure contacting said at least one semiconductor fin and said single crystalline silicon-carbon alloy layer and including an oxide of a silicon-containing semiconductor material in an upper portion thereof.
4. The method of claim 3 , wherein an upper portion of said shallow trench isolation structure is located above a horizontal plane, including an interface between said single crystalline silicon-carbon alloy layer and said substrate.
5. The method of claim 3 further comprising wherein a lower portion of said semiconductor fin has a variable width that decreases with a vertical distance from a horizontal plane including an interface between said silicon-carbon alloy layer and said at least one semiconductor fin, and an upper portion of said at least one semiconductor fin has a uniform width that is equal to a minimum width of said lower portion of said at least one semiconductor fin.
6. The method of claim 3 , wherein a first sidewall of said at least one semiconductor fin is substantially vertical between an interface between said silicon-carbon alloy layer and said at least one semiconductor fin and a top surface of said at least one semiconductor fin, and a second sidewall of said at least one semiconductor fin includes a substantially vertical upper portion and a convex surface that contacts said interface at a non-orthogonal angle.
7. The method of claim 1 , wherein said silicon-containing material portion comprises a horizontal portion in contact with said single crystalline silicon-carbon alloy layer and vertical portions in contact with sidewalls of said single crystalline silicon-germanium alloy layer.
8. The method of claim 7 , further comprising forming a dielectric spacer comprising a dielectric material on sidewalls of said silicon-containing material portion after removal of said hard mask layer and said single crystalline silicon-germanium alloy layer, wherein a top surface of said horizontal portion of said silicon-containing material portion is physically exposed after formation of said dielectric spacer.
9. The method of claim 8 , wherein a top surface of each of said vertical portions of said silicon-containing material portion is physically exposed after formation of said dielectric spacer.
10. The method of claim 8 , wherein said removal of said hard mask layer is selective to said removal of said single crystalline silicon-germanium alloy layer.
11. The method of claim 10 , wherein said removal of said single crystalline silicon-germanium alloy layer is selective to said silicon-containing material portion.
12. The method of claim 8 , further comprising:
converting a region of said horizontal portion of said silicon-containing material portion into a shallow trench isolation structure comprising an oxide of an alloy of silicon and germanium; and
converting a region of said single crystalline silicon-carbon alloy layer into another shallow trench isolation structure comprising an oxide of an alloy of silicon and carbon.
13. The method of claim 12 , further comprising:
converting each upper region of said vertical portions of said silicon-containing material portion into a semiconductor oxide portion while said dielectric spacer is present.
14. The method of claim 13 , further comprising removing said dielectric spacers selective to said semiconductor oxide portion.
15. The method of claim 1 , further comprising forming a fin cap dielectric portion on an upper surface of said at least one semiconductor fin.
16. The method of claim 15 , wherein said fin cap dielectric portion comprises an oxide of a semiconductor material in said semiconductor fin and laterally protrudes outward from vertical planes including sidewalls of said at least one semiconductor fin.
17. The method of claim 1 , wherein said at least one semiconductor fin comprises forming a pair of semiconductor fins having the same width.