Inducing device variation for security applications
A Physical Unclonable Function (PUF) semiconductor device includes a semiconductor substrate, and regions, with implant regions and covered regions, in the semiconductor substrate. A hardmask covers a first covered region and a second covered. The first implant region having a first concentration of ions, and at least one second implant region having a second concentration that is less than the first concentration. First and second FETs are formed on the regions. The first and second FETs have a voltage threshold mismatch with respect to one another based on the first region and the at least one second region.
1. A method of forming a Physically Unclonable Function (PUF) semiconductor device, the method comprising:
defining a first and second region on a substrate, the first region includes a first implant region and a first covered region subject to being covered, the second region includes a second implant region and a second covered region subject to being covered, the first implant region has a first width, the second implant region has a second width, and the first width is greater than the second width;
forming a shallow trench isolation (STI) in the substrate, wherein the STI is on adjacent sides of the first region and adjacent sides of the second region;
forming a patterned mask on the first covered region and on the second covered region;
forming a first implant well in the first implant region and a second implant well in the second implant region;
annealing the first implant well and the second implant well, wherein the first implant region and the first covered region have a first uniform dopant concentration, and the second implant region and the second covered region have a second uniform dopant concentration, wherein the first uniform dopant concentration is greater than the second uniform dopant concentration;
forming a first device on the first region and a second device on the second region, wherein the method is performed so that a difference in the first uniform doping concentration and the second uniform doping concentration varies in dependence on a difference between the first width and the second width; and
wherein the method is performed so that random variation in the method of forming the semiconductor device results in the first implant region having the first width, and the second implant region having the second width.
2. The method of claim 1 , wherein the first region and the second region are separated by the STI.
3. The method of claim 1 , wherein forming the patterned mask further comprises:
forming a mask layer covering an entirety of the first region and an entirety of the second region; and
removing a portion of the mask layer from above the first implant region and the second implant region, wherein the patterned mask is a portion of the mask layer remaining on the first covered region and on the second covered region.
4. The method of claim 1 , further comprising:
removing the patterned mask from above the first covered region and the second covered region.
5. The method of claim 1 , wherein the first implant region has a different dopant concentration than the first covered region and the second implant region has a different dopant concentration than the second covered region.
6. The method of claim 1 , wherein the first implant well is formed using ion implementation.
7. The method of claim 1 , wherein the first device on the first region is a metal-oxide-semiconductor field-effect transistor (MOSFET) device and the second device on the second region is a MOSFET device.
8. The method of claim 1 , wherein the first device has a greater threshold voltage value than a threshold voltage value of the second device.
9. The method of claim 1 , wherein the random variation includes random variation in a placement of the patterned mask.
10. The method of claim 1 , wherein the random variation includes random variation in an etching of the patterned mask.