Methods to thin down RMG sidewall layers for scalability of gate-last planar CMOS and FinFET technology

1. A method comprising:

forming a first titanium nitride (TiN) layer on side and bottom surfaces of each of a n-type field effect transistor (nFET) and a p-type FET (pFET) replacement metal gate (RMG) trench;

forming a first amorphous silicon (a-Si) layer over the first TiN layer;

implanting a first oxygen gas (O 2 ) vertically in the first a-Si layer;

removing the first a-Si layer and first TiN layer from the side surfaces of the RMG trenches followed by the first a-Si layer from the bottom surfaces of the RMG trenches;

forming a second TiN layer on the side and bottom surfaces of the RMG trenches;

forming a second a-Si layer over the second TiN layer;

implanting a second O 2 vertically in the second a-Si layer;

removing sequentially the second a-Si layer and second TiN layer from the side surfaces of the RMG trenches, the second a-Si layer from the bottom surfaces of the RMG trenches, and a remainder of the second TiN layer from only the nFET RMG trench;

forming a Ti layer on side and bottom surfaces of the RMG trenches;

implanting aluminum (Al) or carbon (C) in the Ti layer vertically and annealing; and

filling the RMG trenches with Al or tungsten (W).

2. The method according to claim 1 , further comprising forming a tantalum nitride (TaN) layer on side and bottom surfaces of the RMG trenches prior to forming the second TiN layer.

3. The method according to claim 2 , further comprising forming the TaN layer to a thickness of 10 angstrom (Å) to 15 Å and the second TiN layer to a thickness of 2 nanometer (nm) to 6 nm.

4. The method according to claim 1 , comprising forming each of the first and second a-Si layers to a thickness of 2 nm to 5 nm.

5. The method according to claim 1 , comprising performing each of the first and second O 2 implants at a dosage of 1e15 per centimeter squared (cm −2 ) to 1e16 cm −2 and at an energy of 5 kiloelectron volt (keV) to 10 keV.

6. The method according to claim 1 , comprising removing the first a-Si layer by:

wet stripping the first a-Si layer and the first TiN layer from the side surfaces of the RMG trenches;

annealing the RMG trenches;

performing a wet dilute hydrofluoric acid (DHF) dip; and

stripping the first a-Si layer from the bottom surfaces of the RMG trenches.

7. The method according to claim 1 , comprising removing the second a-Si layer by:

wet stripping the second a-Si layer and the second TiN layer from the side surfaces of the RMG trenches;

performing a wet DHF dip; and

wet stripping a remainder of the second a-Si layer.

8. The method according to claim 1 , comprising forming the Ti layer to a thickness of 6 nm to 12 nm.

9. The method according to claim 1 , further comprising implanting the Al or C in the Ti layer at a dose of 1E15 to 1E16 cm −2 .

10. The method according to claim 9 , wherein the titanium aluminum (TiAl) or titanium carbon (TiC) layers are formed to a thickness of 60 Å to 120 Å by the annealing.

11. A method comprising:

forming a first titanium nitride (TiN) layer on side and bottom surfaces of each of a n-type field effect transistor (nFET) and a p-type FET (pFET) replacement metal gate (RMG) trench;

forming a first amorphous silicon (a-Si) layer to a thickness of 2 nanometer (nm) to 5 nm over the first TiN layer;

implanting a first oxygen gas (O 2 ) vertically in the first a-Si layer at a dosage of 1e15 per centimeter squared (cm −2 ) to 1e16 cm −2 and at an energy of 5 kiloelectron volt (keV) to 10 keV;

removing the first a-Si layer and first TiN layer from the side surfaces of the RMG trenches followed by the first a-Si layer from the bottom surfaces of the RMG trenches;

forming a second TiN layer to a thickness 2 nm to 6 nm on the side and bottom surfaces of the RMG trenches;

forming a second a-Si layer to a thickness of 2 nm to 5 nm over the second TiN layer;

implanting a second O 2 vertically in the second a-Si layer at a dosage of 1e15 cm −2 to 1e16 cm −2 and at an energy of 5 keV to 10 keV;

removing sequentially the second a-Si layer and second TiN layer from the side surfaces of the RMG trenches, the second a-Si layer from the bottom surfaces of the RMG trenches, and a remainder of the second TiN layer from only the nFET RMG trench;

forming a Ti layer on side and bottom surfaces of the RMG trenches;

implanting aluminum (Al) or carbon (C) in the Ti layer vertically and annealing; and

filling the RMG trenches with Al or tungsten (W).

12. The method according to claim 11 , further comprising forming a tantalum nitride (TaN) layer on side and bottom surfaces of the RMG trenches prior to forming the second TiN layer.

13. The method according to claim 12 , comprising forming the TaN layer to a thickness of 10 angstrom (Å) to 15 Å.

14. The method according to claim 11 , comprising removing the first a-Si layer by:

wet stripping the first a-Si layer and the first TiN layer from the side surfaces of the RMG trenches;

annealing the RMG trenches;

performing a wet dilute hydrofluoric acid (DHF) dip; and

stripping the first a-Si layer from the bottom surfaces of the RMG trenches.

15. The method according to claim 11 , comprising removing the second a-Si layer by:

wet stripping the second a-Si layer and the second TiN layer form the side surfaces of the RMG trenches;

performing a wet DHF dip; and

wet stripping a remainder of the second a-Si layer.

16. The method according to claim 11 , comprising forming the Ti layer to a thickness of 6 nm to 12 nm.

17. The method according to claim 11 , wherein TiAl or TiC layers are formed to a thickness of 60 Å to 120 Å by the annealing.