Integrated circuit product comprising lateral and vertical FinFet devices
One example of a novel integrated circuit product disclosed herein includes, among other things, a lateral FinFET device comprising a first gate structure having a first upper surface positioned above a semiconductor substrate and a vertical FinFET device comprising a second gate structure having a second upper surface positioned above the semiconductor substrate, wherein the first upper surface of the first gate structure is positioned at a first height level above a reference surface of the semiconductor substrate and the second upper surface of the second gate structure is positioned at a second height level above the reference surface of the semiconductor substrate, the first height level being greater than the second height level.
1. An integrated circuit product, comprising:
a lateral FinFET device comprising a first gate structure having a first upper surface positioned above a semiconductor substrate; and
a vertical FinFET device comprising a second gate structure having a second upper surface positioned above said semiconductor substrate, wherein said first upper surface of said first gate structure is positioned at a first height level above a horizontally-oriented reference surface of said semiconductor substrate, said second upper surface of said second gate structure is positioned at a second height level above said reference surface of said semiconductor substrate, said first height level being greater than said second height level.
2. The product of claim 1 , further comprising:
a first source/drain region for said vertical FinFET device that is positioned vertically above a channel region of said vertical FinFET device; and
a second source/drain region for said vertical FinFET device that is positioned at least partially below said channel region of said vertical FinFET device.
3. The product of claim 1 , wherein said first and second gate structures are comprised of at least one layer of metal.
4. The product of claim 1 , wherein said first and second gate structures are comprised of the same materials.
5. The product of claim 1 , further comprising a source/drain region for said vertical FinFET device that is positioned in said semiconductor substrate at least under a channel region of said vertical FinFET device.
6. The product of claim 2 , further comprising:
a first gate contact structure that is conductively coupled to said first gate structure;
a second gate contact structure that is conductively coupled to said second gate structure; and
a first source/drain contact structure that is conductively coupled to said first source/drain region of said vertical FinFET device.
7. The product of claim 6 , wherein said first source/drain contact region is a source region for said vertical FinFET device.
8. The product of claim 6 , wherein said first source/drain contact region is a drain region for said vertical FinFET device.
9. The product of claim 1 , further comprising a layer of insulating material positioned under said first and second gate structures, wherein, relative to said reference surface of said semiconductor substrate, a first portion of said layer of insulating material that is positioned under said first gate structure has a first upper surface that is located at a first height level and a second portion of said layer of insulating material that is positioned under said second gate structure has a second upper surface that is located at a second height level, said first height level being greater than said second height level.
10. An integrated circuit product, comprising:
a lateral FinFET device comprising a first gate structure positioned above a semiconductor substrate;
a vertical FinFET device comprising a second gate structure positioned above said semiconductor substrate; and
a layer of insulating material positioned under said first and second gate structures, wherein, relative to a horizontally-oriented reference surface of said semiconductor substrate, a first portion of said layer of insulating material that is positioned under said first gate structure has a first upper surface that is located at a first height level and a second portion of said layer of insulating material that is positioned under said second gate structure has a second upper surface that is located at a second height level, said first height level being greater than said second height level.
11. The product of claim 10 , further comprising:
a first source/drain region for said vertical FinFET device that is positioned vertically above a channel region of said vertical FinFET device; and
a second source/drain region for said vertical FinFET device that is positioned at least partially below said channel region of said vertical FinFET device.
12. The product of claim 10 , wherein said first and second gate structures are comprised of at least one layer of metal.
13. The product of claim 10 , wherein said first and second gate structures are comprised of the same materials.
14. The product of claim 10 , further comprising a source/drain region for said vertical FinFET device that is positioned in said semiconductor substrate at least under a channel region of said vertical FinFET device.
15. The product of claim 11 , further comprising:
a first gate contact structure that is conductively coupled to said first gate structure;
a second gate contact structure that is conductively coupled to said second gate structure; and
a first source/drain contact structure that is conductively coupled to said first source/drain region of said vertical FinFET device.
16. The product of claim 15 , wherein said first source/drain contact region is a source region for said vertical FinFET device.
17. The product of claim 15 , wherein said first source/drain contact region is a drain region for said vertical FinFET device.
18. An integrated circuit product, comprising:
a lateral FinFET device comprising a first gate structure having a first upper surface positioned above a semiconductor substrate;
a vertical FinFET device comprising a second gate structure having a second upper surface positioned above said semiconductor substrate, wherein said first and second gate structures are comprised of the same materials and wherein said first upper surface of said first gate structure is positioned at a first height level above a horizontally-oriented reference surface of said semiconductor substrate, said second upper surface of said second gate structure is positioned at a second height level above said reference surface of said semiconductor substrate, said first height level being greater than said second height level; and
a layer of insulating material positioned under said first and second gate structures, wherein, relative to said horizontally-oriented reference surface of said semiconductor substrate, a first portion of said layer of insulating material that is positioned under said first gate structure has a first upper surface that is located at a first height level and a second portion of said layer of insulating material that is positioned under said second gate structure has a second upper surface that is located at a second height level, said first height level being greater than said second height level.
19. The product of claim 18 , further comprising:
a first source/drain region for said vertical FinFET device that is positioned in said semiconductor substrate at least under a channel region of said vertical FinFET device;
a first gate contact structure that is conductively coupled to said first gate structure;
a second gate contact structure that is conductively coupled to said second gate structure; and
a first source/drain contact structure that is conductively coupled to said first source/drain region of said vertical FinFET device.
20. The product of claim 19 , wherein said first source/drain contact region is a source region for said vertical FinFET device.