Method for creating self-aligned compact contacts in an IC device meeting fabrication spacing constraints
Methods for forming a self-aligned gate-cut in close proximity to a gate contact and the resulting device are disclosed. Embodiments include providing a substrate with silicon fins and a metal gate with a nitride-cap perpendicular to and over the fins, with source/drain regions, each with an oxide-cap, on the fins on opposite sides of the gate; forming parallel dielectric lines, separated from each other, perpendicular to and over the gate; forming a photoresist over the parallel dielectric lines, forming an opening in the photoresist exposing a nitride-cap between two fins; removing the exposed nitride-cap exposing an underlying metal gate; removing the exposed metal gate and a remainder of the photoresist; forming low-k dielectric lines between the parallel dielectric lines; removing sections of the parallel dielectric lines; forming perpendicular interconnects between the low-k dielectric lines; removing a remainder of the parallel dielectric lines forming trenches; and filling the trenches with metal.
1. A method comprising:
providing a silicon (Si) substrate with silicon fins and at least one metal gate, each metal gate having a nitride-cap perpendicular to and over the silicon fins, with source/drain (S/D) regions on the silicon fins on opposite sides of each gate and an oxide-cap on each S/D region;
forming parallel dielectric lines separated from each other perpendicular to and over the at least one gate;
forming a first photoresist over the parallel dielectric lines and forming an opening in the photoresist to expose at least one of the nitride-caps between two silicon fins;
removing the exposed at least one nitride-cap to expose an underlying metal gate;
removing the exposed underlying metal gate and a remainder of the first photoresist layer, after removing the exposed at least one nitride cap to expose the underlying gate;
forming parallel low-k dielectric lines adjacent to and in between the parallel dielectric lines;
removing sections of the parallel dielectric lines;
forming perpendicular interconnects between the parallel low-k dielectric lines;
removing a remainder of the parallel dielectric lines forming trenches; and
forming a metal layer in the trenches.
2. The method according to claim 1 , further comprising:
forming a second photoresist layer on the parallel low-k dielectric lines and the perpendicular interconnects and in the trenches prior to forming the metal layer;
removing sections of the second photoresist layer to expose oxide-caps; and
removing the exposed oxide-caps and a remainder of the second photoresist layer.
3. The method according to claim 2 , further comprising:
forming a third photoresist layer on the parallel low-k dielectric lines and the perpendicular interconnects and in the trenches;
removing sections of the third photoresist layer to expose at least one of the nitride-caps;
removing the exposed at least one nitride-cap, after removing sections of the third photoresist layer to expose the at least one of the nitride caps, to form nitride-cap cavities, wherein each of the nitride-cap cavities is adjacent to a gate cavity; and
removing a remainder of the third photoresist layer.
4. The method according to claim 1 , wherein forming the metal layer comprises:
forming the metal layer on the parallel low-k dielectric lines and the perpendicular interconnects and in the trenches; and
performing a chemical mechanical polishing of the metal layer to be substantially coplanar with an upper surface of the low-k dielectric lines.
5. The method according to claim 1 , comprising forming each of the parallel dielectric lines by forming an amorphous Si layer on the upper surface of the Si substrate and a silicon-nitride (SiN) layer on upper surface of the amorphous Si layer.
6. The method according to claim 5 , further comprising forming a silicon dioxide layer on the SiN layer of the parallel dielectric lines.
7. The method according to claim 5 , wherein the SiN layer is thicker than the nitride-cap.
8. The method according to claim 1 , wherein each of the S/D regions is recessed and includes a metal contact.
9. The method according to claim 1 , further comprising:
forming dielectric spacers on opposite sides of each metal gate, separating each metal gate and its nitride-cap from adjacent S/D regions and oxide-caps, respectively.
10. A method comprising:
providing a substrate with silicon fins and at least one metal gate, each metal gate having a nitride-cap perpendicular to and over the silicon fins, with source/drain (S/D) regions on the fins on opposite sides of each gate and an oxide-cap on each S/D region;
forming parallel dielectric lines separated from each other perpendicular to and over the at least one gate;
forming a first photoresist over the parallel dielectric lines and forming an opening in the photoresist to expose at least one nitride-cap between two fins;
removing the exposed nitride-cap to expose an underlying metal gate;
removing the exposed metal gate and a remainder of the first photoresist layer;
forming parallel low-k dielectric lines adjacent to and in between the parallel dielectric lines;
removing sections of the parallel dielectric lines;
forming perpendicular interconnects between the parallel low-k dielectric lines;
removing a remainder of the parallel dielectric lines forming trenches;
forming a second photoresist layer on the parallel low-k dielectric lines and the perpendicular interconnects and in the trenches prior to forming the metal layer;
removing sections of the second photoresist layer to expose oxide-caps;
removing the exposed oxide-caps and a remainder of the second photoresist layer;
forming a third photoresist layer on the parallel low-k dielectric lines and the perpendicular interconnects and in the trenches;
removing sections of the third photoresist layer to expose at least one of the nitride-caps;
removing the exposed nitride-caps to form nitride-cap cavities, wherein each of the nitride-cap cavities is adjacent to a gate cavity;
removing a remainder of the third photoresist layer; and
forming a metal layer in the trenches.
11. The method according to claim 10 , wherein forming the metal layer comprises:
forming the metal layer on the parallel low-k dielectric lines and the perpendicular interconnects and in the trenches; and
performing a chemical mechanical polishing of the metal layer to be substantially coplanar with an upper surface of the low-k dielectric lines.
12. The method according to claim 10 , comprising forming each of the parallel dielectric lines by forming an amorphous Si layer on the upper surface of the Si substrate and a silicon-nitride (SiN) layer on upper surface of the amorphous Si layer.
13. The method according to claim 12 , further comprising forming a silicon dioxide layer on the SiN layer of the parallel dielectric lines.
14. The method according to claim 10 , wherein each of the S/D regions is recessed and includes a metal contact.
15. The method according to claim 10 , further comprising:
forming dielectric spacers on opposite sides of each metal gate, separating the metal gate and nitride-cap from adjacent S/D regions and oxide-caps, respectively.