Silicon-on-nothing FinFETs
View Patent ↗A semiconductor device includes an insulator formed within a void to electrically isolate a fin from an underlying substrate. The void is created by removing a doped sacrificial layer formed between the substrate and a fin layer. The sacrificial layer is doped to allow for a thicker layer relative to an un-doped layer of substantially similar composition. The doped sacrificial layer thickness may be between 10 nm and 250 nm and may be carbon doped silicon-germanium. The thicker sacrificial layer allows for a thicker insulator so as to provide adequate electrical isolation between the fin and the substrate. During formation of the void, the fin may be supported by a dummy gate. The semiconductor structure may also include a bulk region that has at least a maintained portion of the doped sacrificial layer.
1. A method of fabricating a semiconductor device, the method comprising:
forming an epitaxial carbon doped silicon germanium (SiGe:C) sacrificial portion upon a substrate;
forming a fin portion upon the SiGe:C sacrificial portion;
creating a void by removing the SiGe:C sacrificial portion between the substrate and the fin portion, and;
forming an insulator within the void, the insulator electrically isolating the fin portion from the substrate.
2. The method of claim 1 wherein the fin portion is epitaxial silicon.
3. The method of claim 1 wherein the SiGe:C sacrificial portion is doped to allow for a thicker sacrificial portion relative to an un-doped sacrificial portion of substantially similar composition.
4. The method of claim 1 further comprising:
forming a dummy gate to support the fin portion prior to creating the void.
5. The method of claim 1 wherein the SiGe:C sacrificial portion has a thickness between 10 and 250 nm.
6. The method of claim 1 further comprising:
maintaining a bulk portion of the SiGe:C sacrificial layer in a bulk region.
7. The method of claim 2 wherein forming the SiGe:C sacrificial portion and forming the fin portion further comprises:
patterning a SiGe:C sacrificial layer formed upon the substrate and a epitaxial silicon layer formed upon the SiGe:C sacrificial layer.
8. A semiconductor device comprising:
an epitaxial carbon doped silicon germanium (SiGe:C) sacrificial layer upon a substrate upon, and;
an insulator formed within a void that electrically isolates a fin from the substrate, wherein the void is formed by removing the sacrificial layer between the substrate and the fin.
9. The semiconductor device of claim 8 further comprising:
an epitaxial silicon portion upon the epitaxial doped sacrificial layer.
10. The semiconductor device of claim 8 wherein the doped sacrificial layer is doped to allow for a thicker sacrificial layer relative to an un-doped sacrificial layer of substantially similar composition.
11. The semiconductor device of claim 8 further comprising:
a dummy gate that supports the fin.
12. The semiconductor device of claim 8 wherein the doped sacrificial layer has a thickness between 10 and 250 nm.
13. The semiconductor device of claim 8 further comprising:
a bulk region comprising at least a maintained portion of the doped sacrificial layer.
14. The design structure of claim 8 further comprising:
a dummy gate that supports the fin.
15. The design structure of claim 8 wherein the doped sacrificial layer has a thickness between 10 and 250 nm.
16. The design structure of claim 8 further comprising:
a bulk region comprising at least a maintained portion of the doped sacrificial layer.
17. The semiconductor device of claim 9 wherein the epitaxial SiGe:C sacrificial layer and the epitaxial silicon portion are patterned to form the fin.
18. A design structure embodied in a machine readable storage medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:
an epitaxial carbon doped silicon germanium (SiGe:C) sacrificial layer upon a substrate upon, and;
an insulator formed within a void that electrically isolates a fin from the substrate, wherein the void is formed by removing the sacrificial layer between the substrate and the fin.
19. The design structure of claim 18 further comprising:
an epitaxial silicon portion upon the epitaxial doped sacrificial layer.
20. The design structure of claim 18 wherein the doped sacrificial layer is doped to allow for a thicker sacrificial layer relative to an un-doped sacrificial layer of substantially similar composition.