Patent Assignment
Reel/Frame 049612/0211
Assignment of Assignor's Interest
Recorded: 2019-06-27
Pages: 20
Assignor
GLOBALFOUNDRIES INC.
Executed: 2018-11-26
Assignee
ALSEPHINA INNOVATIONS INC.
303 TERRY FOX DRIVE, SUITE 300, OTTAWA, K2K 3J1, CANADA
Covered Properties
(329)
Pod Swapping Internal to Tool Run Time
Current-Aligned Auto-Generated Non-Equiaxial Hole Shape for Wiring
Silicon Germanium Heterojunction Bipolar Transistor Having Interstitial Trapping Layer in Base Region
Semiconductor Structure Having Undercut-Gate-Oxide Gate Stack Enclosed by Protective Barrier Material
Method of Reducing Contamination by Providing an Etch Stop Layer at the Substrate Edge
Electrically Programmable Resistor
Method of Forming Semiconductor Device
Segregating Wafer Carrier Types in Semiconductor Storage Devices
Method of Enhancing Lithography Capabilities During Gate Formation in Semiconductors Having a Pronounced Surface Topography
Strained Mos Device and Methods for Its Fabrication
Method for semiconductor wafer fabrication utilizing a cleaning substrate
Semiconductor Transistors Having Reduced Distances Between Gate Electrode Regions
Post Chemical Mechanical Polishing Etch for Improved Time Dependent Dielectric Breakdown Reliability
Structure and Methods of Forming Contact Structures
Selective Etching Bath Methods
Method to Increase Effective Mosfet Width
Fuse and Pad Stress Relief
Pfet with Tailored Dielectric and Related Methods and Integrated Circuit
Methods of Forming Tubular Objects
Method and Structure to Control Thermal Gradients in Semiconductor Wafers During Rapid Thermal Processing
Methods for Forming a Composite Pattern Including Printed Resolution Assist Features
Method and Apparatus for Fabricating a High-Performance Band-Edge Complementary Metal-Oxide-Semiconductor Device
Semiconductor Device Having a Grain Orientation Layer
Chemical Oxide Removal of Plasma Damaged Sicoh Low K Dielectrics
Device Component Forming Method with a Trim Step Prior to Sidewall Image Transfer (Sit) Processing
Apparatus for Applying a Layer to a Hydrophobic Surface
Method for Producing Self-Aligned Mask, Articles Produced by Same and Composition for Same
Slurryless Mechanical Planarization for Substrate Reclamation
Reduction of Silicide Formation Temperature on Sige Containing Substrates
Method and a Semiconductor Device Comprising a Protection Layer for Reducing Stress Relaxation in a Dual Stress Liner Approach
Method and Process for Forming a Self-Aligned Silicide Contact
Test Structure for Detecting via Contact Shorting in Shallow Trench Isolation Regions
Method of Forming a Metal Silicide Layer, Devices Incorporating Metal Silicide Layers and Design Structures for the Devices
Method for Optimizing the Routing of Wafers/Lots Based on Yield
Addition of Ballast Hydrocarbon Gas to Doped Polysilicon Etch Masked by Resist
Multiple Exposure and Single Etch Integration Method
Substantially L-Shaped Silicide for Contact
Method and Apparatus for Angular High Density Plasma Chemical Vapor Deposition
Cmos Gate Structures Fabricated by Selective Oxidation
Integrated Circuits Comprising an Active Transistor Electrically Connected to a Trench Capacitor by an Overlying Contact and Methods of Making
Methods for Retaining Metal-Comprising Materials Using Liquid Chemistry Dispense Systems from Which Oxygen Has Been Removed
Semiconductor Chip with Backside Conductor Structure
Packaging a Semiconductor Wafer
Etching System and Method for Forming Multiple Porous Semiconductor Regions with Different Optical and Structural Properties on a Single Semiconductor Wafer
Semiconductor Chip with Protective Scribe Structure
In Situ Formed Drain and Source Regions in a Silicon/Germanium Containing Transistor Device
Method and Apparatus for Routing Wafer Pods to Allow Parallel Processing
Method for Uniform Nanoscale Film Deposition
Cad Flow for 15NM/22NM Multiple Fine Grained Wimpy Gate Lengths in Sit Gate Flow
Curvilinear Wiring Structure to Reduce Areas of High Field Density in an Integrated Circuit
Gate Etch Optimization Through Silicon Dopant Profile Change
In-Line Stacking of Transistors for Soft Error Rate Hardening
Methods for Fabricating Semiconductor Devices
Interconnect Structure Fabricated Without Dry Plasma Etch Processing
Flexible Job Preparation and Control
Method of Semiconductor Manufacturing for Small Features
Formation of Alloy Liner by Reaction of Diffusion Barrier and Seed Layer for Interconnect Application
Structure and Method to Improve Threshold Voltage of Mosfets Including a High K Dielectric
Interconnect Structures with Ternary Patterned Features Generated from Two Lithographic Processes
Method of Reducing Dislocation-Induced Leakage in a Strained-Layer Field-Effect Transistor by Implanting Blocking Impurity into the Strained-Layer.
Method for Forming Trenches Having Different Widths and the Same Depth
Fabricating Esd Devices Using Mosfet and Ldmos
Method and Structure for Improving Uniformity of Passive Devices in Metal Gate Technology
Multiple Patterning Using Improved Patternable Low-K Dielectric Materials
Mosfet on Silicon-on-Insulator Redx with Asymmetric Source-Drain Contacts
Nanopillar Decoupling Capacitor
Asymmetric Embedded Silicon Germanium Field Effect Transistor
Arranging Through Silicon Vias in Ic Layout
Structure and Method to Minimize Regrowth and Work Function Shift in High-K Gate Stacks
Asymmetric Finfet Device with Improved Parasitic Resistance and Capacitance
Double Patterning Process for Integrated Circuit Device Manufacturing
Methods for Forming Dense Dielectric Layer Over Porous Dielectrics
Method of Generating Uniformly Aligned Well and Isolation Regions in a Substrate and Resulting Structure
Methods for Protecting Film Layers While Removing Hardmasks During Fabrication of Semiconductor Devices
Semiconductor Device and Methods for Fabricating Same
Interconnect Structure Having a via with a via Gouging Feature and Dielectric Liner Sidewalls for Beol Integration
Method for Reworking Antireflective Coating Over Semiconductor Substrate
Alkaline Rinse Agents for Use in Lithographic Patterning
Angle Ion Implant to Re-Shape Sidewall Image Transfer Patterns
Diffusion Sidewall for a Semiconductor Structure
Interconnect Structure Including a Modified Photoresist as a Permanent Interconnect Dielectric and Method of Fabricating Same
Integrated Circuit Including Finfet Rf Switch Angled Relative to Planar Mosfet and Related Design Structure
Passivation Layer Surface Topography Modifications for Improved Integrity in Packaged Assemblies
Enhancing Mosfet Performance by Optimizing Stress Properties
Integrated Circuit and a Method Using Integrated Process Steps to Form Deep Trench Isolation Structures and Deep Trench Capacitor Structures for the Integrated Circuit
Lateral Trench Fets (Field Effect Transistors)
Structure and Method to Create Stress Trench
Efuse Enablement with Thin Polysilicon or Amorphous-Silicon Gate-Stack for Hkmg Cmos
Mosfet with Multiple Fully Silicided Gate and Method for Making the Same
Asymmetric Fet Including Sloped Threshold Voltage Adjusting Material Layer and Method of Fabricating Same
Selective Copper Encapsulation Layer Deposition
Structure for Use in Fabrication of Pin Heterojunction Tfet
Work Function Adjustment in a High-K Gate Electrode Structure After Transistor Fabrication by Using Lanthanum
Method of Forming a Metallization System of a Semiconductor Device by Using a Hard Mask for Defining the via Size
Field Effect Transistor (Fet) and Method of Forming the Fet Without Damaging the Wafer Surface
Cut First Methodology for Double Exposure Double Etch Integration
Overhead Transport Service Vehicle and Method
Methods for Forming Barrier Regions Within Regions of Insulating Material Resulting in Outgassing Paths from the Insulating Material and Related Devices
Finned Semiconductor Device with Oxygen Diffusion Barrier Regions, and Related Fabrication Methods
Transistor Comprising an Embedded Semiconductor Alloy in Drain and Source Regions Extending Under the Gate Electrode
Method and Structure for Gate Height Scaling with High-K/Metal Gate Technology
Mosfets with Reduced Contact Resistance
High-K Dielectric Gate Structures Resistant to Oxide Growth at the Dielectric/Silicon Substrate Interface and Methods of Manufacture Thereof
Die Level Integrated Interconnect Decal Manufacturing Method and Apparatus
Maintaining Integrity of a High-K Gate Stack by an Offset Spacer Used to Determine an Offset of a Strain-Inducing Semiconductor Alloy
Test System and Method of Reducing Damage in Seed Layers in Metallization Systems of Semiconductor Devices
Self-Aligned Contacts
Integrated Circuits Having Backside Test Structures and Methods for the Fabrication Thereof
Tunnel Field Effect Transistor
Integrated Circuit with Replacement Metal Gates and Dual Dielectrics
Lock and Key Through-via Method for Wafer Level 3D Integration and Structures Produced
Dual Damascene-Like Subtractive Metal Etch Scheme
Method for Air Gap Interconnect Integration Using Photo-Patternable Low K Material
Foreign Material Contamination Detection
Establishing a Hydrophobic Surface of Sensitive Low-K Dielectrics of Microstructure Devices by in Situ Plasma Treatment
Interconnect Structure with an Oxygen-Doped Sic Antireflective Coating and Method of Fabrication
Thin Channel Device and Fabrication Method with a Reverse Embedded Stressor
Local Metallization and Use Thereof in Semiconductor Devices
Interconnect Structure and Method of Fabricating
Method and Structure of Forming Silicide and Diffusion Barrier Layer with Direct Deposited Film on Silicon
Contact Optimization for Enhancing Stress Transfer in Closely Spaced Transistors
Enhancing Selectivity During Formation of a Channel Semiconductor Alloy by a Wet Oxidation Process
Methods to Form Self-Aligned Permanent on-Chip Interconnect Structures
Self-Aligned Silicidation for Replacement Gate Process
Integrated Circuit Structure Incorporating a Conductor Layer with Both Top Surface and Sidewall Passivation and a Method of Forming the Integrated Circuit Structure
Raised Source/Drain Field Effect Transistor
Self-Aligned Permanent on-Chip Interconnect Structure Formed by Pitch Splitting
Method for Integrating Multiple Threshold Voltage Devices for Cmos
Cmos Transistors with Stressed High Mobility Channels
Ser Testing for an Ic Chip Using Hot Underfill
Buried Etch Stop Layer in Trench Isolation Structures for Superior Surface Planarity in Densely Packed Semiconductor Devices
Method of Fabricating a Semiconductor Device Using Compressive Material with a Replacement Gate Technique
High Performance Low Power Bulk Fet Device and Method of Manufacture
Process to Fabricate a Metal High-K Transistor Having First and Second Silicon Sidewalls for Reduced Parasitic Capacitance
Asymmetric Finfet Devices
Replacement Metal Gate Structures for Effective Work Function Control
Use of Contacts to Create Differential Stresses on Devices
Method for Forming Semiconductor Fuses in a Semiconductor Device Comprising Metal Gates
Method and Apparatus for Routing Dispatching and Routing Reticles
Method of Forming Enhanced Capacitance Trench Capacitor
Performance Enhancement in Transistors Comprising High-K Metal Gate Stack by Reducing a Width of Offset Spacers
Devices with Gate-to-Gate Isolation Structures and Methods of Manufacture
Integrated Planar and Multiple Gate Fets
Cap Removal in a High-K Metal Gate Electrode Structure by Using a Sacrificial Fill Material
Localized Implant into Active Region for Enhanced Stress
Enhanced Confinement of High-K Metal Gate Electrode Structures by Reducing Material Erosion of a Dielectric Cap Layer Upon Forming a Strain-Inducing Semiconductor Alloy
Germanium-Containing Release Layer for Transfer of a Silicon Layer to a Substrate
Reducing the Creation of Charge Traps at Gate Dielectrics in Mos Transistors by Performing a Hydrogen Treatment
Method for Growing Strain-Inducing Materials in Cmos Circuits in a Gate First Flow
Metallization System of a Semiconductor Device Comprising Rounded Interconnects Formed by Hard Mask Rounding
Strained Semiconductor Devices and Methods of Fabricating Strained Semiconductor Devices
Method of Fabricating Damascene Structures
Patent:
8,119,522 →
Application:
12/941,184 →
Novel Integration Process to Improve Focus Leveling Within a Lot Process Variation
Structure and Method for Replacement Metal Gate Field Effect Transistors
Semiconductor Device Comprising a Capacitor Formed in the Contact Level
Structure and Method to Fabricate a Body Contact
Dopant Marker for Precise Recess Control
Isolation Fet for Integrated Circuit
Vertical Npnp Structure in a Triple Well Cmos Process
Etch Methods for Semiconductor Device Fabrication
Patent:
8,133,814 →
Application:
12/959,943 →
Device Isolation with Improved Thermal Conductivity
Method of Fabricating a Conductive Interconnect Arrangement for a Semiconductor Device
Patent:
8,183,149 →
Application:
12/973,373 →
Method to Control Metal Semiconductor Micro-Structure
Homogeneous Porous Low Dielectric Constant Materials
Metal-Semiconductor Intermixed Regions
Deposition On A Nanowire Using Atomic Layer Deposition
Double Gate Depletion Mode Mosfet
Fabrication of Cmos Transistors Having Differentially Stressed Spacers
Mask and Etch Process for Pattern Assembly
Patent:
8,119,531 →
Application:
13/013,935 →
Method of Fabricating an Embedded Polysilicon Resistor and an Embedded Efuse Isolated from a Substrate
Structure and Method for Manufacturing Device with a V-Shape Channel Nmosfet
Gate Effective-Workfunction Modification for Cmos
Methods for Fabricating Semiconductor Devices
Silicon Germanium Film Formation Method and Structure
Increasing Robustness of a Dual Stress Liner Approach in a Semiconductor Device by Applying a Wet Chemistry
Methods for Fabricating a Cmos Integrated Circuit Having a Dual Stress Layer (Dsl)
Stress Enhanced Transistor Devices and Methods of Making
Methods for Forming Copper Diffusion Barriers for Semiconductor Interconnect Structures
Fabrication of Devices Having Different Interfacial Oxide Thickness via Lateral Oxidation
Middle of Line Structures
Method of Reducing Contamination by Providing a Removable Polymer Protection Film During Microstructure Processing
Method of Patterning Semiconductor Structure and Structure Thereof
Barrier Trench Structure and Methods of Manufacture
Electromigration Resistant Aluminum-Based Metal Interconnect Structure
Fin-Fet Device and Method and Integrated Circuits Using Such
Enhanced Diffusion Barrier for Interconnect Structures
Method of Improving Memory Cell Device by Ion Implantation
Method and System for Extracting Samples After Patterning of Microstructure Devices
Apparatus for Applying Solder to Semiconductor Chips Using Decals with Aperatures Present Therein
Methods of Forming a Pmos Device with in Situ Doped Epitaxial Source/Drain Regions
Semiconductor Device Including an Asymmetric Feature, and Method of Making the Same
Fabrication of Field-Effect Transistors with Atomic Layer Doping
Field Effect Resistor for Esd Protection
Methods of Forming Semiconductor Devices with Replacement Gate Structures
Patent:
8,357,978 →
Application:
13/230,360 →
Semiconductor Chip with Backside Conductor Structure
Chamfered Corner Crackstop for an Integrated Circuit Chip
Blanket Short Channel Roll-Up Implant with Non-Angled Long Channel Compensating Implant Through Patterned Opening
Methods of Forming and Programming an Electronically Programmable Resistor
E-Fuses Containing at Least One Underlying Tungsten Contact for Programming
Method and Structure to Reduce Fet Threshold Voltage Shift Due to Oxygen Diffusion
Integrated Circuit Having Back Gating, Improved Isolation and Reduced Well Resistance and Method to Fabricate Same
Patent:
8,445,356 →
Application:
13/343,819 →
Layout to Minimize Fet Variation in Small Dimension Photolithography
Diffusion Sidewall for a Semiconductor Structure
Gate Etch Optimization Through Silicon Dopant Profile Change
Method of Fabricating Damascene Structures
Semiconductor Transistors Having Reduced Distances Between Gate Electrode Regions
Method and Structure for Gate Height Scaling with High-K/Metal Gate Technology
Structure and Methods of Forming Contact Structures
Integrated Circuit and a Method Using Integrated Process Steps to Form Deep Trench Isolation Structures and Deep Trench Capacitor Structures for the Integrated Circuit
Structure and Method to Improve Threshold Voltage of Mosfets Including a High K Dielectric
Breakdown Voltage Multiplying Integration Scheme
Asymmetric Fet Including Sloped Threshold Voltage Adjusting Material Layer and Method of Fabricating Same
Field Effect Transistor (Fet) and Method of Forming the Fet Without Damaging the Wafer Surface
Bottom-Up Plating of Through-Substrate Vias
Metal High-K Transistor Having Silicon Sidewalls for Reduced Parasitic Capacitance
Enhanced Capacitance Trench Capacitor
Method and Apparatus for Angular High Density Plasma Chemical Vapor Deposition
Semiconductor-On-Oxide Structure and Method of Forming
Semiconductor Structures and Methods of Manufacture
Method for Keyhole Repair in Replacement Metal Gate Integration Through the Use of a Printable Dielectric
Integrated Circuits Comprising an Active Transistor Electrically Connected to a Trench Capacitor by an Overlying Contact
Self-Aligned Permanent on-Chip Interconnect Structure Formed by Pitch Splitting
Finfet with Enhanced Embedded Stressor
Passivation Layer Surface Topography Modifications for Improved Integrity in Packaged Assemblies
Method and Structure for Reworking Antireflective Coating Over Semiconductor Substrate
Printed Transistor and Fabrication Method
Asymmetric FinFET devices
Dopant Marker for Precise Recess Control
Epitaxial Semiconductor Resistor With Semiconductor Structures On Same Substrate
Structure and Method to Modulate Threshold Voltage for High-K Metal Gate Field Effect Transistors (Fets)
Methods for Forming Barrier Regions Within Regions of Insulating Material Resulting in Outgassing Paths from the Insulating Material and Related Devices
Method for Shaping a Laminate Substrate
Method for Shaping a Laminate Substrate
Dual Damascene Dual Alignment Interconnect Scheme
Method of Manufacturing Scaled Equivalent Oxide Thickness Gate Stacks in Semiconductor Devices and Related Design Structure
Semiconductor Device Fabrication Methods
Nanopillar Decoupling Capacitor
Semiconductor Device with Epitaxial Source/Drain Facetting Provided at the Gate Edge
Integrated Circuit and Method for Fabricating the Same Having a Replacement Gate Structure
Homogeneous Porous Low Dielectric Constant Materials
Tunnel Field Effect Transistor
Fabrication of Devices Having Different Interfacial Oxide Thickness via Lateral Oxidation
Silicon Germanium (Sige) Heterojunction Bipolar Transistor (Hbt)
Device and Method for Forming Sharp Extension Region with Controllable Junction Depth and Lateral Overlap
Interconnect Structure and Method of Fabricating
Method of Replacement Source/Drain for 3D Cmos Transistors
Vertical Npnp Structure in a Triple Well Cmos Process
Germanium-Containing Release Layer for Transfer of a Silicon Layer to a Substrate
Method for Fabricating Silicon-on-Insulator Transistor with Self-Aligned Borderless Source/Drain Contacts
Electronic Fuse Vias in Interconnect Structures
Method and Structure for Finfet with Finely Controlled Device Width
Method to Bridge Extrinsic and Intrinsic Base by Selective Epitaxy in Bicmos Technology
Transistor Formation Using Cold Welding
Laser Doping of Crystalline Semiconductors Using a Dopant-Containing Amorphous Silicon Stack For Dopant Source and Passivation
Transistor Formation Using Cold Welding
Double Trench Well Formation in Sram Cells
Segregating Wafer Carrier Types in Semiconductor Storage Devices
Voltage Contrast Inspection of Deep Trench Isolation
Work Function Adjustment in a High-K Gate Electrode Structure After Transistor Fabrication by Using Lanthanum
Self-Aligned Silicidation for Replacement Gate Process
Methods of Forming a Sidewall Spacer Having a Generally Triangular Shape and a Semiconductor Device Having Such a Spacer
Semiconductor Devices with Replacement Gate Structures Having Conductive Contacts Positioned Therebetween
Photomask Sets for Fabricating Semiconductor Devices
BLANKET EPI SUPER STEEP RETROGRADE WELL FORMATION WITHOUT Si RECESS
Semiconductor Fuses in a Semiconductor Device Comprising Metal Gates
Catalytic Etch With Magnetic Direction Control
Finfet and Method of Fabrication
Structure and Method to Fabricate a Body Contact
Achieving Greater Planarity Between Upper Surfaces of a Layer and a Conductive Structure Residing Therein
Methods of Forming Conductive Copper-Based Structures Using a Copper-Based Nitride Seed Layer Without a Barrier Layer and the Resulting Device
Patent:
8,753,975 →
Application:
13/757,288 →
Methods of Forming Copper-Based Nitride Liner/Passivation Layers for Conductive Copper Structures and the Resulting Device
Method for Fabricating a Semiconductor Integrated Circuit with a Litho-Etch, Litho-Etch Process for Etching Trenches
Method for Growing Strain-Inducing Materials in Cmos Circuits in a Gate First Flow
Enhanced Diffusion Barrier for Interconnect Structures
Semiconductor Fabrication Method Using Stop Layer
Controlled Metal Extrusion Opening in Semiconductor Structure and Method of Forming
Electroless Fill of Trench in Semiconductor Structure
Electronic Fuse with Resistive Heater
Electrical Leakage Reduction in Stacked Integrated Circuits Having Through-Silicon-via (Tsv) Structures
Localized Implant into Active Region for Enhanced Stress
Self-Aligned Contacts
System for Separately Handling Different Size Foups
Method of Forming a Dielectric Film
Using Sacrificial Oxide Layer for Gate Length Tuning and Resulting Device
Reduction of Oxide Recesses for Gate Height Control
Silicon-Based Electronics with Disabling Feature
Bulk Semiconductor Fins with Self-Aligned Shallow Trench Isolation Structures
Substrate Bonding with Diffusion Barrier Structures
Method to Control Metal Semiconductor Micro-Structure
Method for Manufacturing Silicon-Based Electronics with Disabling Feature
Semiconductor Device with Distinct Multiple-Patterned Conductive Tracks on a Same Level
Alignment of Integrated Circuit Chip Stack
Finfet Structures Having Silicon Germanium and Silicon Channels
Forming Alignment Mark and Resulting Mark
Dielectric Filler Fins for Planar Topography in Gate Level
High Voltage Lateral Double-Diffused Metal Oxide Semiconductor Field Effect Transistor (Ldmosfet) Having a Deep Fully Depleted Drain Drift Region
Fin Pitch Scaling and Active Layer Isolation
Methods of Forming Gate Structures for Transistor Devices for Cmos Applications
Elemental Semiconductor Material Contact for High Electron Mobility Transistor
Alleviation of the Corrosion Pitting of Chip Pads
Wafer to Wafer Alignment by Led/Lsd Devices
Test Macro for Use with a Multi-Patterning Lithography Process
Silicon-On-Nothing Finfets
Embedded on-Chip Security
Gate Height Uniformity in Semiconductor Devices
Integrated Circuits with Protected Resistors and Methods for Fabricating the Same
Devices and Methods of Forming Finfets with Self Aligned Fin Formation
Finfet Fabrication Method
Electrically Isolated SiGe FIN Formation By Local Oxidation
Base Profile of Self-Aligned Bipolar Transistors for Power Amplifier Applications
Common Fill of Gate and Source and Drain Contacts
Nozzle Alignment Tool for a Fluid Dispensing Apparatus
Dual Silicide Integration with Laser Annealing
Metallic Mask Patterning Process for Minimizing Collateral Etch of an Underlayer
Methods for Fabricating Integrated Circuits with Fully Silicided Gate Electrode Structures
Methods for Fabricating Finfet Integrated Circuits Using Laser Interference Lithography Techniques
Replacement Low-K Spacer
Method of Making Semiconductor Device with Distinct Multiple-Patterned Conductive Tracks on a Same Level
Method of Fabricating an Interlayer Structure of Increased Elasticity Modulus
Patent:
9,076,645 →
Application:
14/272,554 →
Integrated Inductor
Patent:
9,129,843 →
Application:
14/302,880 →
Mounting Structure and Mounting Structure Manufacturing Method
Removing Metal Fills in a Wiring Layer
Fin Field-Effect Transistor (Finfet) Device Formed Using a Single Spacer, Double Hardmask Scheme
Patent:
9,159,630 →
Application:
14/330,063 →
Finfet with Enhanced Embedded Stressor
Layout to Minimize Fet Variation in Small Dimension Photolithography
Achieving Greater Planarity Between Upper Surfaces of a Layer and a Conductive Structure Residing Therein
Electronic Fuse Vias in Interconnect Structures
Double Trench Well Formation in Sram Cells
Method for Keyhole Repair in Replacement Metal Gate Integration Through the Use of a Printable Dielectric
Related Assignments
(5)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Dec 11, 2013
From: GUO, DECHAO; HAENSCH, WILFRIED E.A.; HAN, SHU-JEN; LIN, CHUNG-HSUN
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 031756/0273 →
Assignment of Assignor's Interest
Sep 3, 2015
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: GLOBALFOUNDRIES U.S. 2 LLC
Reel/Frame 036550/0001 →
Assignment of Assignor's Interest
Oct 5, 2015
From: GLOBALFOUNDRIES U.S. 2 LLC; GLOBALFOUNDRIES U.S. INC.
To: GLOBALFOUNDRIES INC.
Reel/Frame 036779/0001 →
Assignment of Assignor's Interest
Jul 16, 2020
From: ALSEPHINA INNOVATIONS, INC.
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 053351/0839 →
Release of Security Interest
Nov 20, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES INC.
Reel/Frame 054636/0001 →