Method of manufacturing scaled equivalent oxide thickness gate stacks in semiconductor devices and related design structure
View Patent ↗A method of forming a semiconductor device is disclosed. The method includes: forming a dielectric region on a substrate; annealing the dielectric region in an environment including ammonia (NH 3 ); monitoring a nitrogen peak of at least one of the substrate and the dielectric region during the annealing; and adjusting a parameter of the environment based on the monitoring of the nitrogen peak.
1. A method of forming a semiconductor device, the method comprising:
forming a dielectric region on a substrate;
annealing the dielectric region in an environment including ammonia (NH 3 );
monitoring a nitrogen peak of at least one of the substrate and the dielectric region during the annealing; and
adjusting a parameter of the environment based on the monitoring of the nitrogen peak.
2. The method of claim 1 , wherein the annealing is performed at a pressure less than about 20 Torr.
3. The method of claim 2 , wherein the annealing is performed at a pressure less than about 10 Torr.
4. The method of claim 1 , further comprising monitoring a nitrogen (N) depth profile of at least one of the substrate and the dielectric region.
5. The method of claim 4 , wherein the monitoring the N depth profile includes using an X-ray Photoelectron Spectroscopy (XPS) to measure N concentration along a depth of the substrate or the dielectric region.
6. The method of claim 1 , wherein the monitoring the nitrogen peak includes determining a relation between amounts of silicon nitride (SiN) and hafnium nitride (HfN) in the semiconductor device.
7. The method of claim 1 , wherein the adjusting the parameter of the environment includes adjusting a pressure in the environment during the annealing.
8. The method of claim 1 , wherein the adjusting the parameter of the environment includes adjusting a concentration of NH 3 in the environment during the annealing.
9. The method of claim 1 , further comprising forming an interfacial region on the substrate, the interfacial region configured to be disposed between the substrate and the dielectric region.
10. The method of claim 1 , wherein the dielectric region includes a high dielectric constant (high-K) dielectric region.
11. A method of forming a semiconductor device, the method comprising:
annealing a substrate and a high-K dielectric region in an environment including ammonia (NH 3 );
monitoring a nitrogen (N) profile in at least one of the substrate and the high-K dielectric during the annealing; and
adjusting a parameter of the environment based on the monitoring of the N profile.
12. The method of claim 11 , wherein the annealing process is performed at a pressure less than about 20 Torr and the dielectric region includes a high dielectric constant (high-K) dielectric region.
13. The method of claim 11 , wherein the monitoring is performed via an X-ray Photoelectron Spectroscopy (XPS) configured to determine a nitrogen (N) depth profile of at least one of the substrate and the dielectric region.
14. The method of claim 11 , wherein the monitoring the nitrogen profile includes determining a relation between amounts of silicon nitride (SiN) and hafnium nitride (HfN) in the semiconductor device.
15. The method of claim 11 , wherein the adjusting the parameter of the environment includes manipulating at least one of a pressure in the environment, a temperature in the environment, and a concentration of NH 3 in the environment.