Double trench well formation in SRAM cells

1. A device comprising:

a silicon (Si) substrate;

a deep n-well or deep p-well formed in the Si substrate;

a first p-well or first n-well, respectively, formed above the deep n-well or deep p-well;

a plurality of deep trenches having a first depth extending into the deep n-well or deep p-well;

a plurality of first and second shallow trenches each first and second shallow trench having a second depth less than the first depth, a first or second shallow trench being formed between a pair of adjacent deep trenches;

an oxide filling each deep trench and each of the first and second shallow trenches;

a silicon fin on each side of each of the first and second shallow trenches; and

a second n-well or a second p-well formed through and around a bottom portion of each first or second shallow trench, respectively.

2. The device according to claim 1 , wherein the first depth ranges from 1500 Å to 5000 Å.

3. The device according to claim 1 , wherein the second depth ranges from 700 Å to 3000 Å.

4. The device according to claim 1 , further comprising a p+ or n+ region, respectively, above each second n-well or second p-well on each side of each first or second shallow trench, respectively.

5. The device according to claim 1 , further comprising an n+ or p+ region, respectively, above each second n-well or second p-well on each side of each first or second shallow trench, respectively.

6. The device according to claim 1 , comprising:

wherein the plurality of deep trenches comprises first, second, third, and fourth deep trenches;

wherein a first or second shallow trench being formed between a pair of adjacent deep trenches comprises a first shallow trench between the second and third deep trenches, a second shallow trench between the first and second deep trenches and a second shallow trench between the third and fourth deep trenches; and

wherein a second n-well or a second p-well formed through and around a bottom portion of each first or second shallow trench, respectively, comprises a second n-well formed through and around a bottom portion of the first shallow trench and a second p-well formed through and around a bottom portion of each of the second shallow trenches.

7. The device according to claim 1 , wherein the silicon fins have a pitch of 40 (nanometers) nm to 100 nm and a width of 8 nm to 50 nm.

8. The device according to claim 1 , wherein the silicon fins adjacent opposite sides of each first or second shallow trench are doped with p+ or n+ dopants, respectively, to a depth of 50 Å to 1000 Å.

9. The device according to claim 1 , wherein each second n-well or second p-well has a width of 80 nm.

10. The device according to claim 1 , wherein the plurality of first and second shallow trenches comprises four first shallow trenches and two second shallow trenches to form a static random-access memory (SRAM) cell comprising at least four n-type metal-oxide-semiconductor (NMOS) field effect transistors and at least two p-type metal-oxide-semiconductor (PMOS) field effect transistors.

11. A device comprising:

a silicon (Si) substrate;

a deep n-well or deep p-well formed in the Si substrate;

a first p-well or first n-well formed above the deep n-well or deep p-well, respectively;

a plurality of deep trenches, each filled with an oxide comprising a high aspect ratio process (HARP) material, a spin-on dielectric, or tetraethyl orthosilicate (TEOS) and having a depth of 1500 Å to 5000 Å, extending into the deep n-well or deep p-well;

a plurality of first and second shallow trenches, each first and second shallow trench filled with an oxide and having a depth less than the depth of the deep trenches, a first or second shallow trench being formed between a pair of adjacent deep trenches;

silicon fins on opposite sides of each of the first and second shallow trenches; and

a second n-well or a second p-well formed through and around a bottom portion of each first or second shallow trench, respectively.

12. The device according to claim 11 , wherein each first or second shallow trench has a depth of 700 Å to 3000 Å.

13. The device according to claim 11 , further comprising a p+ or n+ region, respectively, above each second n-well or second p-well on each side of each first or second shallow trench, respectively.

14. The device according to claim 11 , further comprising an n+ or p+ region, respectively, above each second n-well or second p-well on each side of each first or second shallow trench, respectively.

15. The device according to claim 11 , comprising:

wherein the plurality of deep trenches comprises first, second, third, and fourth deep trenches;

wherein a first or second shallow trench being formed between a pair of adjacent deep trenches comprises a first shallow trench between the second and third deep trenches, a second shallow trench between the first and second deep trenches and a second shallow trench between the third and fourth deep trenches; and

wherein a second n-well or a second p-well formed through and around a bottom portion of each first or second shallow trench, respectively, comprises a second n-well formed through and around a bottom portion of the first shallow trench and a second p-well formed through and around a bottom portion of each of the second shallow trenches.

16. The device according to claim 11 , wherein the silicon fins have a pitch of 40 (nanometers) nm to 100 nm and a width of 8 nm to 50 nm.

17. The device according to claim 11 , wherein the silicon fins adjacent opposite sides of each first or second shallow trench are doped with p+ or n+ dopants, respectively, to a depth of 50 Å to 1000 Å.

18. The device according to claim 11 , wherein each second n-well or second p-well has a width of 80 nm.

19. The device according to claim 11 , wherein the plurality of first and second shallow trenches comprises four first shallow trenches and two second shallow trenches to form a static random-access memory (SRAM) cell comprising at least four n-type metal-oxide-semiconductor (NMOS) field effect transistors and at least two p-type metal-oxide-semiconductor (PMOS) field effect transistors.

20. A device comprising:

a silicon (Si) substrate;

a deep n-well or deep p-well formed in the Si substrate;

a first p-well or first n-well, respectively, formed above the deep n-well or deep p-well;

first, second, third, and fourth deep trenches, each filled with an oxide comprising a high aspect ratio process (HARP) material, a spin-on dielectric, or tetraethyl orthosilicate (TEOS) and having a depth of 1500 Å to 5000 Å, extending into the deep n-well or deep p-well;

a first shallow trench between the second and third deep trenches and a second shallow trench between the first and second deep trenches and a second shallow trench between the third and fourth deep trenches, the first and second shallow trenches each filled with an oxide and having a depth of 700 Å to 3000 Å wherein the depth is less than the depth of the deep trenches;

a silicon fin on each side of each of the first and second shallow trenches, the silicon fins having a pitch of 40 (nanometers) nm to 100 nm and a width of 8 nm to 50 nm;

a second n-well formed through and around a bottom portion of the first shallow trench;

a p+ or n+ region above each second n-well;

a second p-well formed through and around a bottom portion of each second shallow trench; and

if a p+ region is formed above each second n-well, then an n+ region is formed above each second p-well, and if an n+ region is formed above each second n-well, then a p+ region is formed above each second n-well, wherein the p+ region and the n+ region are formed to a depth of 50 angstroms to 1000 angstroms.