Patent Assignment
Reel/Frame 053351/0839
Assignment of Assignor's Interest
Recorded: 2020-07-16
Received: 2020-07-16
Pages: 13
Assignor
ALSEPHINA INNOVATIONS, INC.
Executed: 2020-02-11
Assignee
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
NO.8, LI-HSIN RD. 6, HSINCHU SCIENCE PARK,, HSINCHU, TWX, 30078, TAIWAN
Covered Properties
(100)
Curvilinear Wiring Structure to Reduce Areas of High Field Density in an Integrated Circuit
Application:
13/945,678 →
Selective Etching Bath Methods
Application:
13/615,770 →
Silicon Germanium (Sige) Heterojunction Bipolar Transistor (Hbt)
Application:
13/610,641 →
Integrated Circuits Comprising an Active Transistor Electrically Connected to a Trench Capacitor by an Overlying Contact
Application:
13/454,635 →
Metal High-K Transistor Having Silicon Sidewalls for Reduced Parasitic Capacitance
Application:
13/432,395 →
Structure and Method to Improve Threshold Voltage of Mosfets Including a High K Dielectric
Application:
13/409,693 →
Structure and Methods of Forming Contact Structures
Application:
13/405,443 →
Semiconductor Transistors Having Reduced Distances Between Gate Electrode Regions
Application:
13/357,757 →
Methods of Forming and Programming an Electronically Programmable Resistor
Application:
13/295,392 →
Semiconductor Chip with Backside Conductor Structure
Application:
13/239,872 →
Method for Fabricating Semiconductor Devices Using Stress Engineering
Application:
13/236,627 →
Method of Patterning Semiconductor Structure and Structure Thereof
Application:
13/102,007 →
Gate Effective-Workfunction Modification for Cmos
Application:
13/019,949 →
Double Gate Depletion Mode Mosfet
Application:
13/013,311 →
Reducing the Creation of Charge Traps at Gate Dielectrics in Mos Transistors by Performing a Hydrogen Treatment
Application:
12/916,681 →
Cap Removal in a High-K Metal Gate Electrode Structure by Using a Sacrificial Fill Material
Application:
12/905,655 →
Performance Enhancement in Transistors Comprising High-K Metal Gate Stack by Reducing a Width of Offset Spacers
Application:
12/900,578 →
Process to Fabricate a Metal High-K Transistor Having First and Second Silicon Sidewalls for Reduced Parasitic Capacitance
Application:
12/880,478 →
Method of Fabricating Hetero-Junction Bipolar Transistor (Hbt)
Application:
12/732,560 →
Overhead Transport Service Vehicle and Method
Application:
12/706,676 →
Lateral Trench Fets (Field Effect Transistors)
Application:
12/640,192 →
Semiconductor Device and Methods for Fabricating Same
Application:
12/603,353 →
Methods for Forming Dense Dielectric Layer Over Porous Dielectrics
Application:
12/569,077 →
Method of Reducing Dislocation-Induced Leakage in a Strained-Layer Field-Effect Transistor by Implanting Blocking Impurity into the Strained-Layer.
Application:
12/539,235 →
Interconnect Structures with Ternary Patterned Features Generated from Two Lithographic Processes
Application:
12/538,114 →
Structure and Method to Improve Threshold Voltage of Mosfets Including a High K Dielectric
Application:
12/535,183 →
In Situ Formed Drain and Source Regions in a Silicon/Germanium Containing Transistor Device
Application:
12/394,475 →
Centrifugal Method for Filing High Aspect Ratio Blind Micro Vias with Powdered Materials for Circuit Formation
Application:
12/247,894 →
Semiconductor Chip with Backside Conductor Structure
Application:
12/237,568 →
Integrated Circuits Comprising an Active Transistor Electrically Connected to a Trench Capacitor by an Overlying Contact and Methods of Making
Application:
12/186,780 →
Substantially L-Shaped Silicide for Contact
Application:
12/182,212 →
Addition of Ballast Hydrocarbon Gas to Doped Polysilicon Etch Masked by Resist
Application:
12/170,634 →
Mask Forming and Implanting Methods Using Implant Stopping Layer
Application:
12/145,915 →
Polycarbosilane Buried Etch Stops in Interconnect Structures
Application:
12/140,854 →
Test Structure for Detecting via Contact Shorting in Shallow Trench Isolation Regions
Application:
12/140,479 →
Method and Process for Forming a Self-Aligned Silicide Contact
Application:
12/136,885 →
Method and a Semiconductor Device Comprising a Protection Layer for Reducing Stress Relaxation in a Dual Stress Liner Approach
Application:
12/131,429 →
Method of Forming an Embedded Barrier Layer for Protection from Chemical Mechanical Polishing Process
Application:
12/123,799 →
Damascene Wiring Fabrication Methods Incorporating Dielectric Cap Etch Process with Hard Mask Retention
Application:
12/121,378 →
Reduction of Silicide Formation Temperature on Sige Containing Substrates
Application:
12/120,854 →
Opto-Thermal Annealing Methods for Forming Metal Gate and Fully Silicided Gate-Field Effect Transistors
Application:
12/120,286 →
Method for Producing Self-Aligned Mask, Articles Produced by Same and Composition for Same
Application:
12/107,889 →
Eliminating Metal-Rich Silicides Using an Amorphous Ni Alloy Silicide Structure
Application:
12/105,034 →
Apparatus for Applying a Layer to a Hydrophobic Surface
Application:
12/103,110 →
Device Component Forming Method with a Trim Step Prior to Sidewall Image Transfer (Sit) Processing
Application:
12/062,618 →
Chemical Oxide Removal of Plasma Damaged Sicoh Low K Dielectrics
Application:
12/044,245 →
Trench-Edge-Defect-Free Recrystallization by Edge-Angle-Optimized Solid Phase Epitaxy: Method and Applications to Hybrid Orientation Substrates
Application:
12/044,579 →
Gate Effective-Workfunction Modification for Cmos
Application:
12/037,158 →
Multiple Patterning Using Patternable Low-K Dielectric Materials
Application:
12/029,848 →
Methods for Forming a Composite Pattern Including Printed Resolution Assist Features
Application:
12/013,627 →
Semiconductor Automation Buffer Storage Identification System and Method
Application:
11/972,685 →
Double Gate Depletion Mode Mosfet
Application:
11/972,811 →
Integrated Circuit System Employing Multiple Exposure Dummy Patterning Technology
Application:
11/972,809 →
Metal Gate Stack and Semiconductor Gate Stack for Cmos Devices
Application:
11/954,918 →
Deep Trench Semiconductor Structure and Method
Application:
11/942,756 →
Polyconductor Line End Formation and Related Mask
Application:
11/935,714 →
Self Aligned Ring Electrodes
Application:
11/924,073 →
Selective Silicon-on-Insulator Isolation Structure and Method
Application:
11/871,249 →
Structure and Methods of Forming Contact Structures
Application:
11/870,551 →
Process for Interfacial Adhesion in Laminate Structures Through Patterned Roughing of a Surface
Application:
11/862,706 →
Semiconductor Device and Methods for Fabricating Same
Application:
11/846,318 →
Processing with Reduced Line End Shortening Ratio
Application:
11/843,629 →
Method of Making a Semiconductor Structure
Application:
11/841,018 →
Selective Thin Metal Cap Process
Application:
11/841,114 →
Post Chemical Mechanical Polishing Etch for Improved Time Dependent Dielectric Breakdown Reliability
Application:
11/833,283 →
Overhead Transport Service Vehicle and Method
Application:
11/828,657 →
Integrated Circuit Employing Variable Thickness Film
Application:
11/781,664 →
Strained Mos Device and Methods for Its Fabrication
Application:
11/775,619 →
Method of Enhancing Lithography Capabilities During Gate Formation in Semiconductors Having a Pronounced Surface Topography
Application:
11/773,631 →
Structure and Method of Integrating Compound and Elemental Semiconductors for High-Performance Cmos
Application:
11/762,376 →
Method for Reducing Resist Poisoning During Patterning of Silicon Nitride Layers in a Semiconductor Device
Application:
11/742,878 →
Method for semiconductor wafer fabrication utilizing a cleaning substrate
Application:
11/789,157 →
Cmos Gate Conductor Having Cross-Diffusion Barrier
Application:
11/692,402 →
Semiconductor Device Having Structure with Fractional Dimension of the Minimum Dimension of a Lithography System
Application:
11/691,332 →
Chevron Cmos Trigate Structure
Application:
11/689,549 →
Method for Integrating Liner Formation in Back End of Line Processing
Application:
11/673,276 →
Two-Sided Semiconductor-on-Insulator Structures and Methods of Manufacturing the Same
Application:
11/627,653 →
Polycarbosilane Buried Etch Stops in Interconnect Structures
Application:
11/619,502 →
Soft Error Reduction of Cmos Circuits on Substrates with Hybrid Crystal Orientation Using Buried Recombination Centers
Application:
11/618,346 →
Scalable Strained Fet Device and Method of Fabricating the Same
Application:
11/615,153 →
Method of Manufacture of an Integrated Circuit System with Self-Aligned Isolation Structures
Application:
11/614,961 →
Process of Etching a Titanium/Tungsten Surface and Etchant Used Therein
Application:
11/563,858 →
Electrically Programmable Resistor
Application:
11/550,450 →
Test Structure and Method for Detecting via Contact Shorting in Shallow Trench Isolation Regions
Application:
11/469,940 →
Strained Mosfets on Separated Silicon Layers
Application:
11/463,640 →
Chip Dicing
Application:
11/463,348 →
End of Range (Eor) Secondary Defect Engineering Using Chemical Vapor Deposition (Cvd) Substitutional Carbon Doping
Application:
11/462,846 →
Double-Sided Waffle Pack
Application:
11/461,960 →
A Method of Forming an Interconnect Structure Diffusion Barrier with High Nitrogen Content
Application:
11/461,220 →
Semiconductor Structure and Method of Manufacture
Application:
11/382,720 →
Method of Integrating Triple Gate Oxide Thickness
Application:
11/481,213 →
Use of Scanning Theme Implanters and Annealers for Selective Implantation and Annealing
Application:
11/420,819 →
Method and Semiconductor Structure for Monitoring the Fabrication of Interconnect Structures and Contacts in a Semiconductor Device
Application:
11/419,782 →
Method of Forming Substantially L-Shaped Silicide Contact for a Semiconductor Device
Application:
11/383,965 →
Opto-Thermal Annealing Methods for Forming Metal Gate and Fully Silicided Gate Field Effect Transistors
Application:
11/408,522 →
Chemical Oxide Removal of Plasma Damaged Sicoh Low K Dielectrics
Application:
11/308,672 →
Trench-Edge-Defect-Free Recrystallization by Edge-Angle-Optimized Solid Phase Epitaxy: Method and Applications to Hybrid Orientation Substrates
Application:
11/406,123 →
Determining Metrology Sampling Decisions Based on Fabrication Simulation
Application:
11/363,748 →
Selective Incorporation of Charge for Transistor Channels
Application:
11/346,662 →
Structure and Method for Enhanced Triple Well Latchup Robustness
Application:
11/275,644 →