Reducing the creation of charge traps at gate dielectrics in MOS transistors by performing a hydrogen treatment
View Patent ↗By performing a heat treatment on the basis of a hydrogen ambient, exposed silicon-containing surface portions may be reorganized prior to the formation of gate dielectric materials. Hence, the interface quality and the material characteristics of the gate dielectrics may be improved, thereby reducing negative bias temperature instability effects in highly scaled P-channel transistors.
1. A method of forming a gate electrode using a gate replacement technique, the method comprising:
performing a first heat treatment on a silicon-containing semiconductor layer having a dielectric layer formed on its surface in the presence of hydrogen;
forming a first dielectric layer above said silicon-containing semiconductor layer after said first heat treatment;
forming a gate electrode structure above said first dielectric layer and silicon-containing semiconductor layer, the gate electrode being surrounded by a dielectric material;
removing said gate electrode structure and said first dielectric layer beneath said gate electrode structure to expose a surface of said silicon-containing semiconductor layer beneath said gate electrode structure;
performing a second heat treatment on said exposed surface of said silicon-containing semiconductor layer in the presence of hydrogen;
forming a second gate insulation layer on said exposed surface of said silicon-containing semiconductor layer after performing said second heat treatment; and
forming a replacement gate electrode structure above said second gate insulation layer to form said gate electrode, said second gate insulation layer having a thickness differing from a thickness of a first gate insulation layer comprising the dielectric layer and the first dielectric layer.
2. The method of claim 1 , further comprising creating a dopant profile in said silicon-containing semiconductor layer and performing a further heat treatment in the presence of hydrogen after creating said dopant profile.
3. The method of claim 1 , further comprising forming a trench isolation structure in said silicon-containing semiconductor layer prior to forming said first gate insulation layer, wherein a further heat treatment in the presence of hydrogen is performed prior to forming said trench isolation structure.