Method of enhancing lithography capabilities during gate formation in semiconductors having a pronounced surface topography
View Patent ↗In a mesa isolation configuration for forming a transistor on a semiconductor island, an additional planarization step is performed to enhance the uniformity of the gate patterning process. In some illustrative embodiments, the gate electrode material may be planarized, for instance, on the basis of CMP, to compensate for the highly non-uniform surface topography, when the gate electrode material is formed above the non-filled isolation trenches. Consequently, significant advantages of the mesa isolation strategy may be combined with a high degree of scalability due to the enhancement of the critical gate patterning process.
1. A method, comprising:
forming an isolation trench to define an active semiconductor area in a semiconductor layer formed above a substrate;
forming a gate insulation layer on said active semiconductor area;
forming a gate electrode material above said gate insulation layer on said active semiconductor area and within said isolation trench, said gate electrode material having a surface topography;
forming a sacrificial material on said gate electrode material having said surface topography;
planarizing said sacrificial material, wherein planarizing said sacrificial material comprises redistributing material on at least an upper surface of said sacrificial material during a deformable state thereof; and
patterning a gate electrode from said gate electrode material after planarizing said surface topography.
2. The method of claim 1 , further comprising providing an anti-reflective coating and a resist layer above said sacrificial layer.
3. The method of claim 1 , wherein redistributing material on at least an upper surface of said sacrificial material comprises performing a mechanical imprint process, said mechanical imprint process comprising mechanically contacting said sacrificial material by a deforming surface.
4. The method of claim 3 , wherein said deforming surface comprises one of a mechanical die roll having a curved surface and a mechanical die having a planar contact surface.
5. The method of claim 1 , wherein redistributing material on at least an upper surface of said sacrificial material comprises controlling a residual thickness of said sacrificial material above said active semiconductor area on the basis of a predefined target value.
6. A method, comprising:
forming a gate electrode above a semiconductor layer formed above a substrate;
forming a sacrificial material above said semiconductor layer and said gate electrode, said sacrificial material having a surface topography and at least laterally enclosing said gate electrode;
planarizing said surface topography of said sacrificial material; and
after planarizing said surface topography of said sacrificial material, forming an isolation trench in said semiconductor layer to define an active semiconductor area for said gate electrode.
7. The method of claim 6 , wherein said sacrificial material is planarized by a polishing process.
8. The method of claim 6 , wherein said sacrificial material is planarized by contacting said sacrificial material with a deforming surface.
9. The method of claim 6 , further comprising patterning said sacrificial material and using said patterned sacrificial material as an etch mask for forming said isolation trench.
10. The method of claim 9 , further comprising forming a hard mask layer prior to forming said sacrificial material and patterning said hard mask layer on the basis of said patterned sacrificial material.
11. A method comprising:
forming a material layer above an active semiconductor area defined by an isolation trench formed in a semiconductor layer, said material layer comprising a gate insulation layer, a gate electrode material formed above said gate insulation layer, and a sacrificial material layer formed above said gate electrode material;
planarizing said material layer to provide a substantially planar surface topography, wherein planarizing said material layer comprises performing a mechanical imprint process; and
patterning said planarized material layer to form a gate electrode above said active semiconductor area.
12. The method of claim 11 , wherein said semiconductor layer is formed on a buried insulating layer.
13. The method of claim 11 , wherein performing said mechanical imprint process comprises redistributing material on at least an upper surface of said material layer during a deformable state thereof by mechanically contacting said material layer by a deforming surface.
14. The method of claim 13 , wherein said deforming surface comprises one of a mechanical die roll having a curved surface and a mechanical die having a planar contact surface.
15. A method, comprising:
forming an isolation trench to define an active semiconductor area in a semiconductor layer formed above a substrate of a semiconductor device;
forming a gate electrode material above said active semiconductor area defined by said isolation trench, said gate electrode material having a surface topography;
planarizing said surface topography of said gate electrode material;
patterning a gate electrode from said gate electrode material after planarizing said surface topography; and
forming sidewall spacer structures on all sidewalls of said active semiconductor area.
16. The method of claim 15 , further comprising forming a cover layer above said gate electrode, said active semiconductor area, and said substrate of said semiconductor device.
17. The method of claim 16 , further comprising forming a contact opening to expose a contact area of said semiconductor device, wherein forming said contact opening comprises using said cover layer as an etch stop layer.
18. The method of claim 16 , wherein said cover layer comprises a stressed material layer.
19. The method of claim 15 , wherein said sidewall spacer structures formed on sidewalls of said active semiconductor area do not extend to sidewalls of said gate electrode.
20. The method of claim 15 , further comprising forming separate sidewall spacer structures on sidewalls of said gate electrode.