Patent Assignment
Reel/Frame 023120/0426
AFFIRMATION OF PATENT ASSIGNMENT
Recorded: 2009-08-18
Received: 2009-08-18
Pages: 127
Assignor
ADVANCED MICRO DEVICES, INC.
Executed: 2009-06-30
Assignee
GLOBALFOUNDRIES INC.
P.O. BOX 309, UGLAND HOUSE, GRAND CAYMAN, KYX, KY1-1104, CAYMAN ISLANDS
Covered Applications
(100)
Accelerometer Guided Processing Unit
App. No. 12/468,355
→
TECHNIQUE FOR REDUCING SILICIDE NON-UNIFORMITIES IN POLYSILICON GATE ELECTRODES BY AN INTERMEDIATE DIFFUSION BLOCKING LAYER
App. No. 12/464,917
→
CMOS DEVICE COMPRISING MOS TRANSISTORS WITH RECESSED DRAIN AND SOURCE AREAS AND A SI/GE MATERIAL IN THE DRAIN AND SOURCE AREAS OF THE PMOS TRANSISTOR
App. No. 12/464,161
→
THREE-DIMENSIONAL TRANSISTOR WITH DOUBLE CHANNEL CONFIGURATION
App. No. 12/425,462
→
SEMICONDUCTOR DEVICE COMPRISING ISOLATION TRENCHES INDUCING DIFFERENT TYPES OF STRAIN
App. No. 12/419,500
→
REDUCING CONTAMINATION OF SEMICONDUCTOR SUBSTRATES DURING BEOL PROCESSING BY PERFORMING A DEPOSITION/ETCH CYCLE DURING BARRIER DEPOSITION
App. No. 12/418,857
→
REDUCING IMPLANT DEGRADATION IN TILTED IMPLANTATIONS BY SHIFTING IMPLANTATION MASKS
App. No. 12/417,978
→
SEMICONDUCTOR DEVICE COMPRISING A CHIP INTERNAL ELECTRICAL TEST STRUCTURE ALLOWING ELECTRICAL MEASUREMENTS DURING THE FABRICATION PROCESS
App. No. 12/417,749
→
SEMICONDUCTOR DEVICE COMPRISING METAL LINES WITH A SELECTIVELY FORMED DIELECTRIC CAP LAYER
App. No. 12/401,887
→
METHOD AND SYSTEM FOR AUTOMATIC GENERATION OF THROUGHPUT MODELS FOR SEMICONDUCTOR TOOLS
App. No. 12/400,174
→
METHOD FOR REDUCING DEFECTS OF GATE OF CMOS DEVICES DURING CLEANING PROCESSES BY MODIFYING A PARASITIC PN JUNCTION
App. No. 12/397,574
→
IN SITU FORMED DRAIN AND SOURCE REGIONS IN A SILICON/GERMANIUM CONTAINING TRANSISTOR DEVICE
App. No. 12/394,475
→
ERROR DETECTION DEVICE AND METHODS THEREOF
App. No. 12/394,701
→
METHOD AND APPARATUS FOR USING MULTIPLE PROTOCOLS ON A COMMUNICATION LINK
App. No. 12/392,735
→
METHOD OF FORMING A SEMICONDUCTOR DEVICE
App. No. 12/390,907
→
COLD TEMPERATURE CONTROL IN A SEMICONDUCTOR DEVICE
App. No. 12/390,816
→
METHOD AND SYSTEM FOR PERFORMING A DOUBLE PASS NTH FAIL BITMAP OF A DEVICE MEMORY
App. No. 12/389,748
→
SEMICONDUCTOR CHIP WITH PROTECTIVE SCRIBE STRUCTURE
App. No. 12/388,064
→
METAL OXIDE SEMICONDUCTOR DEVICES HAVING DOPED SILICON-COMPROMISING CAPPING LAYERS AND METHODS FOR FABRICATING THE SAME
App. No. 12/388,094
→
METHOD AND SYSTEM FOR SEMICONDUCTOR PROCESS CONTROL AND MONITORING BY USING PCA MODELS OF REDUCED SIZE
App. No. 12/388,060
→
SEMICONDUCTOR TRANSISTOR DEVICE HAVING AN ASYMMETRIC EMBEDDED STRESSOR CONFIGURATION, AND RELATED MANUFACTURING METHOD
App. No. 12/371,846
→
SEMICONDUCTOR DEVICE INCLUDING ANALOG CIRCUITRY HAVING A PLURALITY OF DEVICES OF REDUCED MISMATCH
App. No. 12/367,106
→
METHOD TO REDUCE MOL DAMAGE ON NISI
App. No. 12/366,378
→
WIRE BONDING ON REACTIVE METAL SURFACES OF A METALLIZATION OF A SEMICONDUCTOR DEVICE BY PROVIDING A PROTECTIVE LAYER
App. No. 12/365,963
→
METHOD AND SYSTEM FOR MONITORING A PREDICTED PRODUCT QUALITY DISTRIBUTION
App. No. 12/366,211
→
PROCESSOR INSTRUCTIONS FOR IMPROVED AES ENCRYPTION AND DECRYPTION
App. No. 12/365,543
→
METHODS FOR FABRICATING FINFET STRUCTURES HAVING DIFFERENT CHANNEL LENGTHS
App. No. 12/365,300
→
ETCHING SYSTEM AND METHOD FOR FORMING MULTIPLE POROUS SEMICONDUCTOR REGIONS WITH DIFFERENT OPTICAL AND STRUCTURAL PROPERTIES ON A SINGLE SEMICONDUCTOR WAFER
App. No. 12/361,736
→
STRESSED FIELD EFFECT TRANSISTOR AND METHODS FOR ITS FABRICATION
App. No. 12/360,961
→
METHODS FOR FABRICATING MOS DEVICES HAVING EPITAXIALLY GROWN STRESS-INDUCING SOURCE AND DRAIN REGIONS
App. No. 12/359,764
→
PROCESSOR POWER MANAGEMENT AND METHOD
App. No. 12/356,624
→
COMPUTER SYSTEM COMPRISING A SECURE BOOT MECHANISM ON THE BASIS OF SYMMETRIC KEY ENCRYPTION
App. No. 12/355,900
→
REDUCING PATTERNING VARIABILITY OF TRENCHES IN METALLIZATION LAYER STACKS WITH A LOW-K MATERIAL BY REDUCING CONTAMINATION OF TRENCH DIELECTRICS
App. No. 12/355,112
→
METHOD FOR ENCAPSULATING A HIGH-K GATE STACK BY FORMING A LINER AT TWO DIFFERENT PROCESS TEMPERATURES
App. No. 12/355,250
→
APPLICATION PARTITIONING ACROSS A VIRTUALIZED ENVIRONMENT
App. No. 12/354,435
→
SOI TRANSISTOR WITH FLOATING BODY FOR INFORMATION STORAGE HAVING ASYMMETRIC DRAIN/SOURCE REGIONS
App. No. 12/353,431
→
PSEUDO BANDGAP VOLTAGE REFERENCE CIRCUIT
App. No. 12/349,810
→
Processing Acceleration on Multi-Core Processor Platforms
App. No. 12/344,882
→
OPTIMIZATION OF APPLICATION POWER CONSUMPTION AND PERFORMANCE IN AN INTEGRATED SYSTEM ON A CHIP
App. No. 12/338,459
→
ENHANCED CONTROL OF CPU PARKING AND THREAD RESCHEDULING FOR MAXIMIZING THE BENEFITS OF LOW-POWER STATE
App. No. 12/333,744
→
METHODS FOR PROTECTING GATE STACKS DURING FABRICATION OF SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES FABRICATED FROM SUCH METHODS
App. No. 12/330,292
→
MEMORY DEVICE AND METHOD THEREOF
App. No. 12/330,012
→
METHODS FOR FABRICATING STRESSED MOS DEVICES
App. No. 12/330,296
→
METHOD AND APPARATUS FOR DECOMPRESSION OF BLOCK COMPRESSED DATA
App. No. 12/329,236
→
Framework for Control Flow-Aware Processes
App. No. 12/325,685
→
TRANSACTION BASED VERIFICATION OF A SYSTEM ON CHIP ON SYSTEM LEVEL BY TRANSLATING TRANSACTIONS INTO MACHINE CODE
App. No. 12/324,212
→
ARITHMETIC PROCESSING DEVICE AND METHODS THEREOF
App. No. 12/274,996
→
EXECUTE-ONLY MEMORY AND MECHANISM ENABLING EXECUTION FROM EXECUTE-ONLY MEMORY FOR MINIVISOR
App. No. 12/272,951
→
Alternate Address Space to Permit Virtual Machine Monitor Access to Guest Virtual Address Space
App. No. 12/272,946
→
MINIVISOR ENTRY POINT IN VIRTUAL MACHINE MONITOR ADDRESS SPACE
App. No. 12/272,955
→
INCREASING STRESS TRANSFER EFFICIENCY IN A TRANSISTOR BY REDUCING SPACER WIDTH DURING THE DRAIN/SOURCE IMPLANTATION SEQUENCE
App. No. 12/271,162
→
INTELLIGENT MEMORY BUFFER
App. No. 12/271,213
→
METHOD AND APPARATUS FOR REGULATING POWER CONSUMPTION
App. No. 12/268,531
→
Post Processing of Dynamically Generated Code
App. No. 12/266,192
→
METHODS FOR PROTECTING GATE STACKS DURING FABRICATION OF SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES FABRICATED FROM SUCH METHODS
App. No. 61/111,632
→
SYSTEM FOR DYNAMIC PROGRAM PROFILING
App. No. 12/263,902
→
ETCH STOP LAYER OF REDUCED THICKNESS FOR PATTERNING A DIELECTRIC MATERIAL IN A CONTACT LEVEL OF CLOSELY SPACED TRANSISTORS
App. No. 12/260,147
→
METHOD AND APPARATUS FOR REDUCING SEMICONDUCTOR PACKAGE TENSILE STRESS
App. No. 12/259,357
→
AIR GAP SPACER FORMATION
App. No. 12/258,188
→
METHOD FOR CREATING TENSILE STRAIN BY APPLYING STRESS MEMORIZATION TECHNIQUES AT CLOSE PROXIMITY TO THE GATE ELECTRODE
App. No. 12/257,718
→
WORK BALANCING SCHEDULER FOR PROCESSOR CORES AND METHODS THEREOF
App. No. 12/256,703
→
INTEGRATED CIRCUIT HAVING A MEMORY WITH A PLURALITY OF STORAGE CELLS OF SYNCHRONOUS DESIGN AND CONNECTED TO CLOCK GATING UNITS
App. No. 12/255,366
→
STRESSED MOS DEVICE AND METHODS FOR ITS FABRICATION
App. No. 12/254,682
→
PROTOCOL FOR POWER STATE DETERMINATION AND DEMOTION
App. No. 12/254,650
→
EXECUTING MICRO-CODE INSTRUCTION WITH DELAY FIELD AND ADDRESS OF NEXT INSTRUCTION WHICH IS DECODED AFTER INDICATED DELAY
App. No. 12/253,339
→
SEMICONDUCTOR DEVICE
App. No. 12/251,959
→
MEMORY DEVICE AND METHODS THEREOF
App. No. 12/251,509
→
REGISTER REDUCTION AND LIVENESS ANALYSIS TECHNIQUES FOR PROGRAM CODE
App. No. 12/249,446
→
SEMICONDUCTOR CHIP WITH BACKSIDE CONDUCTOR STRUCTURE
App. No. 12/237,568
→
INTERPOSER INCLUDING VOLTAGE REGULATOR AND METHOD THEREFOR
App. No. 12/236,003
→
FUNCTIONAL BLOCK LEVEL THERMAL CONTROL
App. No. 12/235,155
→
MINIMIZING MEMORY ACCESS CONFLICTS OF PROCESS COMMUNICATION CHANNELS
App. No. 12/212,370
→
METHOD AND APPARATUS FOR MAKING A PROCESSOR SIDEBAND INTERFACE ADHERE TO SECURE MODE RESTRICTIONS
App. No. 12/208,071
→
STRESS ENHANCED MOS CIRCUITS
App. No. 12/208,196
→
METHODS FOR RETAINING METAL-COMPRISING MATERIALS USING LIQUID CHEMISTRY DISPENSE SYSTEMS FROM WHICH OXYGEN HAS BEEN REMOVED
App. No. 12/208,159
→
METHOD OF FORMING ISOLATION REGIONS FOR INTEGRATED CIRCUITS
App. No. 12/205,361
→
SEMICONDUCTOR DEVICE COMPRISING A METAL GATE STACK OF REDUCED HEIGHT AND METHOD OF FORMING THE SAME
App. No. 12/204,395
→
MULTIPROCESSOR COMMUNICATION DEVICE AND METHODS THEREOF
App. No. 12/203,456
→
DEVICE AND PROCESS OF FORMING DEVICE WITH DEVICE STRUCTURE FORMED IN TRENCH AND GRAPHENE LAYER FORMED THEREOVER
App. No. 12/201,801
→
PROCESS OF PATTERNING SMALL SCALE DEVICES
App. No. 12/201,993
→
HARDWARE MONITORING AND DECISION MAKING FOR TRANSITIONING IN AND OUT OF LOW-POWER STATE
App. No. 12/198,974
→
HARDWARE BASED MULTI-DIMENSIONAL ENCRYPTION
App. No. 12/198,239
→
METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE WITH SELF-ALIGNED STRESSOR AND EXTENSION REGIONS
App. No. 12/194,246
→
SOI SUBSTRATES AND DEVICES ON SOI SUBSTRATES HAVING A SILICON NITRIDE DIFFUSION INHIBITION LAYER AND METHODS FOR FABRICATING
App. No. 12/191,861
→
METHODS FOR UNIFORMLY OPTICALLY ANNEALING REGIONS OF A SEMICONDUCTOR SUBSTRATE
App. No. 12/190,332
→
REDUCTION OF MEMORY INSTABILITY BY LOCAL ADAPTATION OF RE-CRYSTALLIZATION CONDITIONS IN A CACHE AREA OF A SEMICONDUCTOR DEVICE
App. No. 12/188,324
→
ESD POWER CLAMP WITH STABLE POWER START UP FUNCTION
App. No. 12/186,630
→
Advanced Synchronization Facility
App. No. 61/084,008
→
METHOD AND APPARATUS FOR NANO PROBING A SEMICONDUCTOR CHIP
App. No. 12/180,989
→
METHOD FOR SELECTIVELY FORMING STRAIN IN A TRANSISTOR BY A STRESS MEMORIZATION TECHNIQUE WITHOUT ADDING ADDITIONAL LITHOGRAPHY STEPS
App. No. 12/179,116
→
TRANSISTOR DEVICE HAVING ASYMMETRIC EMBEDDED STRAIN ELEMENTS AND RELATED MANUFACTURING METHOD
App. No. 12/176,835
→
METAL OXIDE SEMICONDUCTOR DEVICES HAVING IMPLANTED CARBON DIFFUSION RETARDATION LAYERS AND METHODS FOR FABRICATING THE SAME
App. No. 12/176,916
→
METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAVING SELF-ALIGNED CONTACT STRUCTURE ENCLOSED BY AN ISOLATION TRENCH STRUCTURE.
App. No. 12/176,469
→
METHODS FOR REMOVING A METAL-COMPRISING MATERIAL FROM A SEMICONDUCTOR SUBSTRATE
App. No. 12/174,497
→
Solder Interconnect
App. No. 12/173,105
→
INCREASING ELECTROMIGRATION RESISTANCE IN AN INTERCONNECT STRUCTURE OF A SEMICONDUCTOR DEVICE BY FORMING AN ALLOY
App. No. 12/172,555
→
GRID-BASED FRAGMENTATION FOR OPTICAL PROXIMITY CORRECTION IN PHOTOLITHOGRAPHY MASK APPLICATIONS
App. No. 12/170,988
→
Selective Compression Based on Data Type and Client Capability
App. No. 12/169,897
→
TEMPERATURE MONITORING IN A SEMICONDUCTOR DEVICE BY THERMOCOUPLES DISTRIBUTED IN THE CONTACT STRUCTURE
App. No. 12/169,020
→
IN-DIE FOCUS MONITORING WITH BINARY MASK
App. No. 12/167,808
→