Method and apparatus for decompression of block compressed data

1. A method for decompressing data, comprising:

receiving a compressed data stream comprising one or more contiguous variable length blocks, wherein each variable length block comprises:

a plurality of contiguous variable length data fields; and

a tag portion, comprising a plurality of contiguous tag fields corresponding respectively to the plurality of variable length data fields, wherein each tag field stores a tag value specifying a size of a respective variable length data field in the variable length block;

storing a current variable length block of the one or more contiguous variable length data blocks;

executing a single machine instruction of a processor, wherein said executing comprises:

analyzing the tag portion of the current variable length block;

creating a control pattern and storing the control pattern in a first register of the processor, wherein the control pattern is configured to unpack the variable length data fields of the current variable length block into corresponding uniform data fields;

decompressing the plurality of contiguous variable length data fields of the current variable length block using the control pattern, wherein said decompressing operates to decompress the compressed data stream.

2. The method of claim 1 ,

wherein said storing comprises storing the current variable length block in a second register;

wherein said decompressing the plurality of contiguous variable length data fields of the current variable length block comprises:

storing results of said decompressing in a third register of the processor.

3. The method of claim 1 ,

wherein said control pattern indicates if data being deposited in a destination byte of the third register is a copy of a selected source byte or zero values.

4. The method of claim 2 , further comprising:

determining a size of the variable length data field based on said analyzing the tag portion.

5. The method of claim 4 , further comprising:

storing the size of the variable length data field in a fourth register of the processor.

6. The method of claim 1 ,

wherein said creating the control pattern comprises determining offsets indicating starting locations of each of the variable length data fields in the block.

7. The method of claim 1 , further comprising:

determining a next value based on the tag portion, wherein the next value points to a subsequent variable length block of the one or more contiguous variable length blocks; and

storing the next value into a second register of the processor;

wherein the next value is useable to determine a starting location of a subsequent variable length block.

8. The method of claim 1 , further comprising:

performing said storing, said executing, and said decompressing for each of the one or more contiguous variable length blocks.

9. The method of claim 1 , wherein the single machine instruction comprises:

a first input operand comprising a length of the data field of the current variable length block plus 1;

a second input operand comprising an address of the current data block, wherein the address of the current data block points to the tag field of the current variable length block; and

an output operand for returning a routing pattern for the current data block.

10. The method of claim 1 , wherein said executing the single first machine instruction does not reference external memory.

11. The method of claim 1 , wherein the processor has an x86 architecture.

12. The method of claim 1 , wherein the first register comprises:

a multimedia extension register for performing multimedia operations; or

a general purpose register.

13. The method of claim 1 , wherein the processor is configured to operate under an operating system, and wherein the single machine instruction of the processor does not require modification of the operating system to execute.

14. The method of claim 1 , wherein said executing the single machine instruction comprises:

converting the single machine instruction to two or more microcode instructions; and

executing the two or more microcode instructions.

15. A processor, comprising:

an input configured to receive a compressed data stream comprising one or more contiguous variable length blocks, wherein each variable length block comprises:

a plurality of contiguous variable length data fields; and

a tag portion, comprising a plurality of contiguous tag fields corresponding respectively to the plurality of variable length data fields, wherein each tag field stores a tag value specifying a size of a respective variable length data field in the data block;

a first register for storing a current variable length block of the one or more contiguous variable length data blocks;

an execution unit configured to execute a single first machine instruction of the processor to:

analyze the tag portion of the current variable length block;

create a control pattern and store the control pattern in a second register of the processor, wherein the control pattern is configured to unpack the variable length data fields of the current variable length block into corresponding uniform data fields;

wherein the execution unit is further configured to execute one or more second machine instructions to decompress the plurality of contiguous variable length data fields of the current variable length block using the control pattern, wherein said decompressing operates to decompress the compressed data stream.

16. The processor of claim 15 ,

wherein said decompressing comprises storing results of said decompressing in a third register of the processor.

17. The processor of claim 15 ,

wherein the control pattern indicates if data being deposited in a destination byte of the third register is a copy of a selected source byte or zero values.

18. The processor of claim 17 , wherein the execution unit is further configured to execute the single first machine instruction of the processor to:

determine a size of the variable length data field based on said analyzing the tag portion; and

store the size of the variable length data field in a fourth register of the processor.

19. The processor of claim 15 ,

wherein said creating the control pattern comprises determining offsets indicating starting locations of each of the variable length data fields in the block.

20. The processor of claim 15 , wherein the single first machine instruction comprises:

a first input operand comprising a length of the data field of the current variable length block plus 1;

a second input operand comprising an address of the current data block, wherein the address of the current data block points to the tag field of the current variable length block; and

an output operand for returning a routing pattern for the current data block.

21. The processor of claim 15 , wherein said executing the single first machine instruction does not reference external memory.

22. The processor of claim 15 , wherein the processor has an x86 architecture, and wherein the first register comprises:

a multimedia extension register for performing multimedia operations; or

a general purpose register.

23. The processor of claim 15 , wherein the processor is configured to operate under an operating system, and wherein the single first machine instruction of the processor does not require modification of the operating system to execute.

24. The processor of claim 15 , wherein to execute the single first machine instruction of the processor, the execution unit is configured to:

convert the single machine instruction to two or more microcode instructions; and

execute the two or more microcode instructions.