METAL OXIDE SEMICONDUCTOR DEVICES HAVING IMPLANTED CARBON DIFFUSION RETARDATION LAYERS AND METHODS FOR FABRICATING THE SAME
Semiconductor devices and methods for fabricating semiconductor devices are provided. One exemplary method comprises providing a silicon-comprising substrate having a first surface, etching a recess into the first surface, the recess having a side surface and a bottom surface, implanting carbon ions into the side surface and the bottom surface, and forming an impurity-doped, silicon-comprising region overlying the side surface and the bottom surface.
1 . A method for fabricating source and drain regions for a semiconductor device, the method comprising the steps of:
providing a silicon-comprising substrate having a first surface;
etching a recess into the first surface, the recess having a side surface and a bottom surface;
implanting carbon ions into the side surface and the bottom surface; and
forming an impurity-doped, silicon-comprising region overlying the side surface and the bottom surface.
2 . The method of claim 1 , wherein the step of forming comprises forming an ion implanted, impurity-doped, silicon-comprising region.
3 . The method of claim 1 , wherein the step of forming comprises epitaxially growing an in situ doped, silicon-comprising region.
4 . The method of claim 1 , wherein the step of implanting carbon ions comprises the step of implanting carbon ions wherein the bottom surface and a source ion beam axis are oriented relative to each other so that the bottom surface is substantially orthogonal to the source ion beam axis.
5 . The method of claim 1 , wherein the step of implanting carbon ions comprises the step of implanting carbon ions wherein the bottom surface and a source ion beam axis are oriented relative to each other so that an angle therebetween is greater than zero degrees and less than 90 degrees.
6 . The method of claim 1 , further comprising the step of forming a gate stack and offset spacers overlying the silicon-comprising substrate and wherein the step of implanting carbon ions comprises the step of implanting carbon ions using the gate stack and the offset spacers as implant masks.
7 . The method of claim 1 , wherein the step of implanting carbon ions comprises the step of implanting carbon ions using an accelerating voltage in the range of about from 1 keV to 15 keV and a dose range of about from 1×10 13 to 1×10 15 cm −2 .
8 . The method of claim 7 , wherein the step of implanting carbon ions comprises the step of implanting carbon ions using an accelerating voltage of about 5 keV and a dose of about 2×10 14 cm −2 .
9 . The method of claim 1 , wherein the step of implanting carbon ions comprises the step of implanting carbon ions to form a carbon-comprising layer at the side surface and the bottom surface, the carbon-comprising layer having a thickness in the range of about from 10 nm to 30 nm.
10 . The method of claim 1 , wherein the step of forming an impurity-doped, silicon-comprising region comprises epitaxially growing a silicon-comprising region further comprising carbon or germanium.
11 . The method of claim 1 , wherein the step of etching a recess into the first surface comprises etching a recess into the first surface that is in a range of about from 50 nm to 100 nm in depth.
12 . A method of fabricating an MOS transistor on a silicon-comprising substrate having a first surface, the method comprising the steps of:
forming a gate stack comprising a gate electrode having sidewalls, the gate stack disposed on the first surface of the silicon-comprising substrate;
forming offset spacers adjacent the sidewalls of the gate electrode;
etching the first surface of the silicon-comprising substrate using the gate stack and the offset spacers as an etch mask to form recesses in the silicon-comprising substrate, the recesses exposing second surfaces of the silicon-comprising substrate;
implanting carbon ions into the second surfaces of the silicon-comprising substrate using the gate stack and the offset spacers as an ion implantation mask; and
epitaxially forming impurity-doped, silicon-comprising regions in the recesses.
13 . The method of claim 12 , further comprising the step of annealing the substrate using rapid thermal annealing.
14 . The method of claim 12 , further comprising the step of annealing the substrate at a temperature of about from 950° C. to 1100° C. and for a time of from about 5 milliseconds to about 5 seconds.
15 . The method of claim 12 , wherein the step of epitaxially forming impurity-doped, silicon-comprising regions comprises forming impurity-doped, silicon-comprising regions that further comprise carbon or germanium.
16 . The method of claim 12 , wherein the step of implanting carbon ions comprises the step of implanting carbon ions using an accelerating voltage in the range of about from 1 keV to 15 keV and a dose range of about from 1×10 13 to 1×10 15 cm −2 .
17 . The method of claim 16 , wherein the step of implanting carbon ions comprises the step of implanting carbon ions using an accelerating voltage of about 5 keV and a dose of about 2×10 14 cm −2 .
18 . The method of claim 12 , wherein the step of implanting carbon ions comprises the step of implanting carbon ions to form a carbon-comprising layer having a thickness in the range of about from 10 nm to 30 nm.
19 . The method of claim 18 , wherein the step of implanting carbon ions comprises the step of implanting carbon ions to form a carbon-comprising layer having a thickness of about 20 nm.
20 . An MOS transistor comprising:
a silicon substrate having a surface;
an epitaxially-grown, impurity-doped region disposed at the surface of the silicon substrate; and
a carbon-comprising region interposed between the surface of the silicon substrate and the epitaxially-grown, impurity-doped region.