Method to reduce MOL damage on NiSi
View Patent ↗Transistor devices are formed with nickel silicide layers formulated to prevent degradation upon removal of overlying stress liners. Embodiments include transistors with nickel silicide layers having a platinum composition gradient increasing in platinum content toward the upper surfaces thereof, i.e., increasing in platinum in a direction away from the gate electrode and source/drain regions. Embodiments include forming a first layer of nickel having a first amount of platinum and forming, on the first layer of nickel, a second layer of nickel having a second amount of platinum, the second weight percent of platinum being greater than the first weight percent. The layers of nickel are then annealed to form a nickel silicide layer having the platinum composition gradient increasing in platinum toward the upper surface. The platinum concentration gradient protects the nickel silicide layer during subsequent processing, as during etching to remove overlying stress liners, thereby avoiding a decrease in device performance.
1. A method comprising:
forming a transistor on a substrate, the transistor comprising source/drain regions and a gate electrode;
forming a first layer of nickel, containing a first amount of platinum, over the transistor;
forming a second layer of nickel, containing a second amount of platinum, on the first layer of nickel, wherein the second amount of platinum is greater than the first amount of platinum; and
annealing the first and second layers of nickel to form a layer of nickel silicide over the source/drain regions and the gate electrode, wherein the nickel silicide layer has a platinum composition gradient with platinum increasing in amount in a direction away from the source/drain regions and the gate electrode.
2. The method according to claim 1 , comprising forming the first and second layers of nickel at a combined thickness from about 45 Å to about 100 Å.
3. The method according to claim 2 , comprising forming the first layer of nickel at a thickness of about 60% to about 80% of the combined thickness.
4. The method according to claim 3 , comprising annealing to form the layer of nickel silicide at a thickness of about 100 Å to about 220 Å.
5. The method according to claim 1 , comprising annealing by heating at a temperature of about 340° C. to about 450° C.
6. The method according to claim 5 , comprising annealing by heating at a temperature of about 360° C. to about 400° C.
7. The method according to claim 1 , comprising annealing by:
(a) heating at a first temperature of about 280° C. to about 350° C.;
(b) followed by heating at a second temperature of about 360° C. to about 450° C.
8. The method according to claim 7 , comprising heating at the first temperature of about 300° C. to about 320° C. and heating at the second temperature of about 380° C. to about 420° C.
9. The method according to claim 1 , comprising forming the first layer of nickel with a platinum content of about 8 wt. % to about 12 wt. %.
10. The method according to claim 9 , comprising forming the second layer of nickel with a platinum content of about 30 wt. % to about 70 wt. %.
11. The method according to claim 10 , comprising:
forming the first layer of nickel at a platinum content of about 10 wt. %; and
forming the second layer of nickel at a platinum content of about 30 wt. % to about 50 wt. %.
12. The method according to claim 1 , further comprising forming a capping layer of titanium nitride over the second layer of nickel before annealing.
13. The method according to claim 12 , further comprising:
removing the capping layer after annealing; and
etching to remove unreacted nickel.
14. A method comprising:
forming a P-channel and an N-channel transistor on a silicon substrate, each transistor including a polysilicon gate electrode and source/drain regions formed in the silicon substrate;
depositing a first layer of nickel containing a first amount of platinum on both transistors;
depositing a second layer of nickel having a second amount of platinum on the first layer of nickel, wherein the second amount of platinum is greater than the first amount of platinum;
depositing a titanium nitride capping layer on the second layer of nickel;
annealing the first and second layers of nickel to form a layer of nickel silicide containing platinum having a concentration gradient with platinum increasing in amount in a direction away from the gate electrode and source/drain regions,
etching to remove the capping layer and unreacted nickel;
forming a first stress liner exhibiting high compressive stress over both transistors;
selectively removing the first stress liner from the N-channel transistor;
forming a second stress liner exhibiting high tensile stress over both transistors; and
selectively removing the second stress liner from the P-channel transistor.