IP Library Granted Patent US 7,858,989
Granted Patent B2
US 7,858,989 · App. 12/201,801 · Granted Dec 28, 2010

Device and process of forming device with device structure formed in trench and graphene layer formed thereover

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,858,989
App. No.
12/201,801
Granted
Dec 28, 2010
Kind
B2
Abstract

A graphene-based device is formed with a substrate having a trench therein, a device structure on the substrate and within the trench, a graphene layer over the device structure, and a protective layer over the graphene layer. Fabrication techniques include forming a trench in a substrate, forming a device structure within the trench, forming a graphene layer over the device structure, and forming a protective layer over the graphene layer.

Claims (34)

1. A process comprising:

forming a trench in a substrate;

forming a device structure within the trench;

forming a graphene layer over the device structure; and

forming a protective layer over the graphene layer.

2. The process according to claim 1 , comprising forming the graphene layer by deposition.

3. The process according to claim 1 , comprising forming the graphene layer by growing the graphene layer on the device structure.

4. The process according to claim 1 , comprising forming the graphene layer by transferring a pre-formed layer of graphene onto the device structure.

5. The process according to claim 4 , comprising forming the pre-formed layer of graphene by mechanical exfoliation or chemical synthesis.

6. The process according to claim 1 , comprising forming the graphene layer by forming a layer of graphene material over the device structure, and aligning and patterning the layer of graphene material with the trench as a reference to form the graphene layer.

7. The process according to claim 1 , comprising forming the device structure within the trench by depositing material and patterning metal contacts for source/drain regions and a gate in the trench, providing a dielectric between the metal contacts for the source/drain regions and the gate, and providing the dielectric between the gate and the graphene layer formed over the device structure.

8. The process according to claim 1 , wherein the device structure is a field effect transistor.

9. The process according to claim 1 , comprising forming the device structure within the trench by depositing material and patterning metal contacts for source/drain regions and two adjacent gates in the trench, wherein the graphene layer formed over the device structure is electrically doped.

10. The process according to claim 1 , wherein the device structure is a p-n junction.

11. The process according to claim 1 , wherein the protective layer is formed over the entire graphene layer.

12. The process according to claim 11 , wherein the entire device structure is covered by the graphene layer and the protective layer.

13. The process according to claim 1 , further comprising:

forming an additional device structure over the graphene layer,

wherein the protective layer is formed over the graphene layer and the additional device structure.

14. A graphene-based device comprising:

a substrate having a trench formed therein;

a device structure formed on said substrate and within said trench;

a graphene layer formed over said device structure; and

a protective layer formed over said graphene layer.

15. The device according to claim 14 , wherein said device structure includes metal contacts for source/drain regions and a gate formed on said substrate in said trench, wherein said device structure further includes a dielectric provided between said metal contacts for said source/drain regions and said gate, and wherein said dielectric is provided between said gate and said graphene layer.

16. The device according to claim 14 , wherein said device structure is a field effect transistor.

17. The device according to claim 14 , wherein said device structure includes metal contacts for source/drain regions and two adjacent gates in said trench, and wherein said graphene layer formed over said device structure is electrically doped.

18. The device according to claim 14 , wherein said device structure is a p-n junction.

19. The device according to claim 14 , wherein said protective layer is formed over the entire graphene layer.

20. The device according to claim 19 , wherein the entire device structure is covered by said graphene layer and said protective layer.

21. The device according to claim 14 , wherein said graphene layer is aligned and patterned with said trench as a reference.

22. The device according to claim 1 , further comprising:

an additional device structure formed over said graphene layer,

wherein said protective layer is formed over said graphene layer and said additional device structure.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded May 12, 2021
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 056987/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 20, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES INC.
Reel/Frame 054636/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2020
From: GLOBALFOUNDRIES INC.
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 054633/0001 →
SECURITY AGREEMENT Recorded Nov 29, 2018
From: GLOBALFOUNDRIES INC.
To: WILMINGTON TRUST, NATIONAL ASSOCIATION
Reel/Frame 049490/0001 →