Air gap spacer formation
View Patent ↗Miniaturized complex transistor devices are formed with reduced leakage and reduced miller capacitance. Embodiments include transistors having reduced capacitance between the gate electrode and source/drain contact, as by utilizing a low-K dielectric constant sidewall spacer material. An embodiment includes forming a gate electrode on a semiconductor substrate, forming a sidewall spacer on the side surfaces of the gate electrode, forming source/drain regions by ion implantation, forming an interlayer dielectric over the gate electrode, sidewall spacers, and substrate, and forming a source/drain contact through the interlayer dielectric. The sidewall spacers and interlayer dielectric are then removed. A dielectric material, such as a low-K dielectric material, is then deposited in the gap between the gate electrode and the source/drain contact so that an air gap is formed, thereby reducing the parasitic “miller” capacitance.
1. A method comprising:
forming a gate electrode on a substrate,
forming a sidewall spacer on side surfaces of the gate electrode,
forming a source/drain contact adjacent the sidewall spacer,
removing the sidewall spacer from between the gate electrode and source/drain contact, and
depositing a dielectric material under conditions to achieve low step coverage between the gate electrode and the source/drain contact to form an air gap between the gate electrode and the contact.
2. The method according to claim 1 , wherein the dielectric material has a dielectric constant (k) not greater than about 4.2.
3. The method according to claim 1 , further comprising forming an inter level dielectric before forming the source/drain contact.
4. The method according to claim 3 , further comprising removing the inter level dielectric before depositing the dielectric material to form the air gap.
5. The method according to claim 1 , comprising forming the sidewall spacer with a material having a dielectric constant between about 4 and about 7.
6. The method according to claim 5 , wherein the material comprises silicon nitride.
7. The method according to claim 1 , comprising depositing the dielectric material by plasma enhanced chemical vapor deposition (PECVD).
8. The method according to claim 7 , comprising depositing the dielectric material at a deposition rate greater than about 750 nanometers per minute.
9. The method according to claim 8 , comprising depositing the dielectric material at a pressure greater than about 100 mT.
10. The method according to claim 8 , comprising depositing the dielectric material at an RF power frequency less than about 25 W.
11. The method according to claim 8 , comprising depositing the dielectric material at a temperature less than about 275 C.°.
12. A transistor device comprising:
a gate electrode,
a source/drain contact spaced apart from the gate electrode,
an inter level dielectric having low step coverage over the gate electrode, the source/drain contact, and partially between the gate electrode and source/drain contact, and
an air gap, surrounded by the inter level dielectric, between the gate electrode and the source/drain contact.
13. The transistor device according to claim 12 , wherein the inter level dielectric comprises an oxide or a material having a dielectric constant (K) not greater than about 4.2.
14. The transistor device according to claim 13 , wherein the inter lever dielectric comprises carbon doped silicon dioxide.
15. The transistor device according to claim 12 , wherein the source/drain contact is spaced apart from the gate electrode by less than about 150 Å.
16. The transistor device according to claim 15 , wherein the source/drain contact is spaced from the gate electrode less than about 75 Å.
17. The transistor device as recited in claim 16 , wherein the source/drain contact is spaced from the gate electrode less than about 60 Å.
18. The transistor device according to claim 12 , wherein the air gap has a thickness greater than a thickness of the inter level dielectric divided by the dielectric constant of the inter level dielectric.
19. A method of fabricating a semiconductor device, the method comprising:
forming a gate electrode and source/drain contact spaced apart from the gate electrode over a substrate;
forming a sidewall spacer on a side surface of the gate electrode and depositing a layer of dielectric material so that the space between the gate electrode and source/drain contact is occupied by the sidewall spacer and
dielectric material having combined dielectric constant K 1 ;
removing the sidewall spacer and dielectric material from between the gate electrode and source/drain contact; and
depositing a dielectric material between the gate electrode and source/drain material and controlling deposition conditions to form an air gap between the gate electrode and source/drain contact such the dielectric material and air gap have a combined dielectric constant K 2 less than K 1 .
20. The method according to claim 19 , comprising controlling the deposition conditions such that K 2 is less than K 1 by about 10% to about 75%.