Method of forming a semiconductor device
View Patent ↗Methods for forming a semiconductor device comprising a semiconductor substrate are provided. In accordance with an exemplary embodiment, a method comprises forming a channel layer overlying the semiconductor substrate, forming a channel capping layer having a first surface overlying the channel layer, oxidizing the first surface of the channel capping layer, and depositing a high-k dielectric layer overlying the channel capping layer.
1. A method for forming a semiconductor device comprising a semiconductor substrate, wherein the method comprises the steps of:
forming a channel layer overlying the semiconductor substrate;
forming a channel capping layer overlying the channel layer, the channel capping layer having a first exposed surface;
oxidizing the first exposed surface of the channel capping layer; and
depositing a high-k dielectric layer overlying the channel capping layer, wherein the semiconductor device is an NFET device, and wherein the step of forming the channel layer comprises forming a monocrystalline silicon channel layer, and the method further comprising the step of forming a compressively-stressed layer interposed between the semiconductor substrate and the channel layer.
2. The method of claim 1 , wherein the step of forming the channel layer comprises forming the channel layer comprising a material selected from a group consisting of silicon, SiC, GaAs, InGaAs, SiGe, InP, and Ge.
3. The method of claim 1 , wherein the step of forming the channel capping layer comprises forming the channel capping layer comprising silicon.
4. The method of claim 1 , wherein the step of forming the channel capping layer comprises forming the channel capping layer having a thickness of from about 1 nm to about 4 nm.
5. The method of claim 1 , wherein the step of depositing the high-k dielectric layer comprises depositing the high-k dielectric layer having a dielectric constant greater than about 7.
6. The method of claim 1 , further comprising the step of forming a gate capping layer overlying the dielectric layer.
7. The method of claim 6 , wherein the step of forming the gate capping layer comprises forming the gate capping layer having a composition selected from a group consisting of lanthanum oxides and oxynitrides, hafnium oxides and oxynitrides, zirconium oxides and oxynitrides, magnesium oxides and oxynitrides, aluminum oxides and oxynitrides, titanium oxides and oxynitrides, tantalum oxides and oxynitrides, yttrium oxides and oxynitrides, and a combination thereof.
8. The method of claim 6 , further comprising the step of forming a metal-comprising gate electrode layer overlying the gate capping layer.
9. A method for forming a semiconductor device comprising a semiconductor substrate, wherein the method comprises the steps of:
forming a channel layer overlying the semiconductor substrate;
forming a channel capping layer overlying the channel layer, the channel capping layer having a first exposed surface;
oxidizing the first exposed surface of the channel capping layer; and
depositing a high-k dielectric layer overlying the channel capping layer, wherein the semiconductor substrate further comprises a first outer surface, and the method further comprising the step of forming a recess in the first outer surface of the semiconductor substrate and wherein the step of forming the channel layer comprises forming the channel layer in the recess.
10. A method of fabricating a semiconductor device on a semiconductor substrate having a first region and a second region, the method comprising the steps of:
forming a first semiconductor layer overlying the first region;
forming a compressively-stressed semiconductor layer overlying the second region;
forming a channel capping layer overlying the first region and the second region, the channel capping layer having a first exposed surface;
oxidizing the first exposed surface of the channel capping layer;
depositing a high-k gate insulator layer overlying the channel capping layer; and
forming a first gate capping layer overlying the high-k gate insulator layer in the first region, and a second gate capping layer overlying the high-k gate insulator layer in the second region.
11. The method of claim 10 , wherein the semiconductor substrate comprises a first outer surface in the first region, and the method further comprising the step of forming a recess in the first outer surface of the semiconductor substrate in the first region, wherein the step of forming the first semiconductor layer comprises forming the first semiconductor layer in the recess.
12. The method of claim 10 , wherein the step of forming a first semiconductor layer comprises forming the first semiconductor layer having a composition selected from a group consisting of silicon, InGaAs, GaAs, and SiC.
13. The method of claim 10 , wherein the step of forming the compressively-stressed semiconductor layer comprises forming the compressively-stressed semiconductor layer having a composition selected from a group consisting of SiGe, Ge, and InP.
14. The method of claim 10 , wherein the step of forming the channel capping layer comprises forming the channel capping layer comprising silicon.
15. The method of claim 10 , wherein the first gate capping layer has a composition different from that of the second gate capping layer.
16. The method of claim 10 , further comprising the step of forming a first metal-comprising gate layer overlying the first gate capping layer in the first region, and a second metal-comprising gate layer overlying the second gate capping layer in the second region.
17. The method of claim 16 , wherein the first metal-comprising gate layer has a composition different from that of the second metal-comprising gate layer.