Method for reducing defects of gate of CMOS devices during cleaning processes by modifying a parasitic PN junction
View Patent ↗By incorporating nitrogen into the P-doped regions and N-doped regions of the gate electrode material prior to patterning the gate electrode structure, yield losses due to reactive wet chemical cleaning processes may be significantly reduced.
1. A method of forming a CMOS device, the method comprising:
forming a gate electrode material on a gate insulation layer;
forming a first mask above said gate electrode material, said first mask covering a first portion of said gate electrode material and exposing a second portion of said gate electrode material;
performing a first tilted implantation process to form an N-doped region in said second portion of said gate electrode material, wherein said first mask reduces N-type dopant penetration into a junction region of said gate electrode material between said first and second portions during said first tilted implantation process;
forming a second mask above said gate electrode material, said second mask covering said second portion and exposing said first portion;
performing a second tilted implantation process to form a P-doped region in said first portion of said gate electrode material, wherein said second mask reduces P-type dopant penetration into said junction region during said second tilted implantation process;
forming a first gate electrode from said N-doped region;
forming second gate electrode from said P-doped region; and
performing a wet chemical cleaning process on said first and second gate electrodes.
2. The method of claim 1 , wherein performing said wet chemical cleaning process comprises using a mixture comprised of ammonia (NH 3 ) and hydrogen peroxide (H 2 O 2 ).
3. The method of claim 1 , further comprising introducing an inert species into said junction region.
4. The method of claim 3 , wherein introducing said inert species comprises introducing at least one of xenon, argon and nitrogen.
5. The method of claim 3 , wherein introducing said inert species in said junction region comprises performing a non-masked implantation process.
6. The method of claim 3 , wherein introducing said inert species in said junction region comprises forming an implantation mask to cover at least a portion of said N-doped region and said P-doped region and to expose at least a portion of said junction region, and implanting said inert species into the exposed portion of said junction region.
7. The method of claim 3 , wherein said inert species is introduced after forming said N-doped region and said P-doped region.
8. The method of claim 3 , wherein said inert species is introduced prior to forming said N-doped region and said P-doped region.
9. The method of claim 8 , wherein said inert species is introduced when forming said gate electrode material.