Method for creating tensile strain by applying stress memorization techniques at close proximity to the gate electrode

1. A method, comprising:

forming a first sidewall spacer structure on sidewalls of a gate electrode of an N-channel transistor and a second sidewall spacer structure on sidewalls of a gate electrode of a P-channel transistor in a common patterning sequence, said first and second sidewall spacer structures comprising an etch stop layer and at least one spacer element;

forming drain and source regions of said N-channel transistor by using said first sidewall spacer structure as an implantation mask;

forming drain and source regions of said P-channel transistor by using said second sidewall spacer structure as an implantation mask;

removing said at least one spacer element of each of said first and second sidewall spacer structures selectively to said etch stop layer in a common etch process;

forming a material layer above said N-channel transistor and above said P-channel transistor; and

selectively removing a first portion of said material layer from above said P-channel transistor, and thereafter performing an anneal process in the presence of a second portion of said material layer to re-crystallize said drain and source regions of the N-channel transistor in a strained state.

2. The method of claim 1 , further comprising etching said second portion of said material layer to form a further spacer element at sidewalls of said gate electrode of said N-channel transistor.

3. The method of claim 2 , further comprising forming a metal silicide in said drain and source regions of said N-channel transistor using said further spacer element as a mask.

4. The method of claim 2 , further comprising depositing an offset material layer above at least said second portion of said material layer prior to etching said second portion of said material layer to form said further spacer element from said second portion of said material layer and said offset material layer.

5. The method of claim 1 , further comprising forming shallow drain and source portions of at least said N-channel transistor, and thereafter forming said etch stop layer and a first spacer layer above said N-channel and said P-channel transistors, etching said first spacer layer to form a first spacer element on said gate electrode of each of said N-channel and said P-channel transistors, and performing an implantation process using said first spacer element as a mask.

6. The method of claim 5 , further comprising forming a second spacer element on said first spacer element and using said first and second spacer elements as an implantation mask.

7. The method of claim 6 , wherein removing said at least one spacer element comprises removing said first and second spacer elements in a common etch process.

8. The method of claim 1 , further comprising removing said second portion of said material layer above said N-channel transistor and forming offset spacer elements on said sidewalls of said gate electrodes of said P-channel transistor and said N-channel transistor.

9. A method, comprising:

forming an etch stop layer above a first transistor and a second transistor;

forming at least one spacer element on said etch stop layer at sidewalls of a gate electrode of said first and second transistors;

forming drain and source regions of said first transistor on the basis of said at least one spacer element;

removing said at least one spacer element from said first and second transistors by using said etch stop layer as an etch stop;

forming a material layer above said first and second transistors;

annealing said first and second transistors in the presence of said material layer;

after annealing said first and second transistors, forming a second spacer element from said material layer; and

forming deep drain and source regions of said second transistor on the basis of said second spacer element.

10. The method of claim 9 , further comprising forming drain and source regions of said second transistor on the basis of said at least one spacer element.

11. The method of claim 9 , further comprising forming an offset spacer layer on said material layer prior to forming said second spacer element.

12. The method of claim 9 , further comprising removing said material layer from above said second transistor prior to annealing said first and second transistors.

13. The method of claim 12 , wherein forming said at least one spacer element comprises forming a first spacer element on said etch stop layer and forming a second spacer element on said first spacer element.

14. A method, comprising:

forming a first sidewall spacer structure on sidewalls of a gate electrode of an N-channel transistor and a second sidewall spacer structure on sidewalls of a gate electrode of a P-channel transistor in a common patterning sequence, said first and second sidewall spacer structures comprising an etch stop layer and at least one spacer element;

forming drain and source regions of said N-channel transistor on the basis of said first sidewall spacer structure;

removing said at least one spacer element of each of said first and second sidewall spacer structures selectively to said etch stop layer in a common removal process;

forming a material layer above said N-channel transistor and above said P-channel transistor;

performing an anneal process in the presence of said material layer to re-crystallize said drain and source regions of at least said N-channel transistor in a strained state;

after performing said anneal process, forming a further spacer element on sidewalls of said gate electrodes of said P-channel transistor and said N-channel transistor from said material layer; and

forming deep drain and source regions of said P-channel transistor on the basis of said further spacer element.