Method for fabricating semiconductor devices using stress engineering
View Patent ↗There is provided a method for fabricating a semiconductor device comprising the formation of a first device in the first device region, the first device comprising first diffusion regions. A stressor layer covering the substrate in the first device region and the first device is subsequently formed, the stressor layer having a first stress value. A laser anneal to memorize at least a portion of the first stress value in the first device is carried out followed by an activation anneal after the laser anneal to activate dopants in the first diffusion regions.
1. A method for fabricating a semiconductor device comprising:
providing a substrate comprising a first device region;
forming a first device in the first device region, the first device comprising first diffusion regions;
forming a stressor layer covering the substrate in the first device region and the first device, the stressor layer having a first stress value;
performing a laser anneal to memorize at least a portion of the first stress value in the first device; and
performing an activation anneal after the laser anneal to activate dopants in the first diffusion regions.
2. The method of claim 1 further comprising removing the stressor layer after performing the laser anneal and before performing the activation anneal.
3. The method of claim 2 , wherein the activation anneal comprises a spike anneal.
4. The method of claim 3 , wherein the activation anneal comprises a spike anneal and an activation laser anneal.
5. The method of claim 1 , wherein the activation anneal causes the first diffusion regions to diffuse outward.
6. The method of claim 1 wherein the first device is a transistor of a first carrier type.
7. The method of claim 6 wherein the first device comprises a first gate electrode and the first diffusion regions are disposed within the substrate on opposed sides of the gate electrode.
8. The method of claim 7 , further comprising amorphizing at least a portion of the first gate electrode and the substrate in the first device region before forming the stressor layer, wherein the laser anneal crystallizes amorphized portions of the first gate electrode and substrate.
9. The method of claim 1 , wherein the substrate further comprises a second device region including a second device, the stressor layer covering the substrate in the second device region and the second device during the laser anneal.
10. The method of claim 9 , wherein the first device is a transistor of a first carrier type and the second device is a transistor of a second opposite carrier type.
11. The method of claim 10 , wherein the first device is an NMOS and the second device is a PMOS.
12. The method of claim 1 , wherein the laser annealing step to memorize at least a portion of the first stress value is conducted at a temperature of.