Patent Assignment
Reel/Frame 049669/0775
Assignment of Assignor's Interest
Recorded: 2019-07-02
Pages: 9
Assignor
GLOBALFOUNDRIES SINGAPORE PTE. LTD.
Executed: 2018-11-26
Assignee
ALSEPHINA INNOVATIONS INC.
303 TERRY FOX DRIVE, SUITE 300, OTTAWA, K2K 3J1, CANADA
Covered Properties
(77)
End of Range (Eor) Secondary Defect Engineering Using Substitutional Carbon Doping
Integrated Circuit with Protected Implantation Profiles and Method for the Formation Thereof
Method to Fabricate Aligned Dual Damascene Openings
Method to Form a Contact Hole
Multiple Layer Resist Scheme Implementing Etch Recipe Particular to Each Layer
Methods for Elimination of Arsenic Based Defects in Semiconductor Devices with Isolation Regions
High Density Plasma and Bias Rf Power Process to Make Stable Fsg with Less Free F and Sin with Less H to Enhance the Fsg/Sin Integration Reliability
Method for Cuo Reduction by Using Two Step Nitrogen Oxygen and Reducing Plasma Treatment
Method for Reducing Argon Diffusion from High Density Plasma Films
Laser Activation of Implanted Contact Plug for Memory Bitline Fabrication
Composite Stress Spacer
Integrated Circuit System Using Dual Damascene Process
A Method for Using a Cu Beol Process to Fabricate an Integrated Circuit (Ic) Originally Having an Al Design
Method to Engineer Etch Profiles in Si Substrate for Advanced Semiconductor Devices
Entire Encapsulation of Cu Interconnects Using Self-Aligned Cusin Film
Method of Forming Substantially L-Shaped Silicide Contact for a Semiconductor Device
Integrated Circuit with Protected Implantation Profiles and Method for the Formation Thereof
End of Range (Eor) Secondary Defect Engineering Using Chemical Vapor Deposition (Cvd) Substitutional Carbon Doping
Integrated Circuit System with Carbon and Non-Carbon Silicon
Integrated Circuit System Employing Gate Shield and/or Ground Shield
Method of Integrating Triple Gate Oxide Thickness
Apparatus and Methods for Cleaning and Drying of Wafers
Method of Manufacture of an Integrated Circuit System with Self-Aligned Isolation Structures
Processing with Reduced Line End Shortening Ratio
Implementation of Temperature-Dependent Phase Switch Layer for Improved Temperature Uniformity During Annealing
Method of Forming High-K Dielectric Stop Layer for Contact Hole Opening
Integrated Circuit System Employing Multiple Exposure Dummy Patterning Technology
Integrated Circuit System Employing Stress-Engineered Spacers
Hybrid Orientation Substrate with Stress Layer
An Integrated Circuit Including a Stressed Dielectric Layer with Stable Stress
Method of Forming Shallow Trench Isolation Structures for Integrated Circuits
Integrated Circuit System Employing Backside Energy Source for Electrical Contact Formation
Method for Reducing Sidewall Etch Residue
Method for Fabricating Semiconductor Devices with Shallow Diffusion Regions
Reliable Interconnection
Localized Anneal
Integrated Circuit System with Band to Band Tunneling and Method of Manufacture Thereof
Non-volatile memory using pyramidal nanocrystals as electron storage elements
Semiconductor device with reduced contact resistance and method of manufacturing thereof
Integrated Circuit System with via and Method of Manufacture Thereof
Methods and Structures to Enable Self-Aligned via Etch for Cu Damascene Structure Using Trench First Metal Hard Mask (Tfmhm) Scheme
Patent:
8,114,769 →
Application:
12/982,956 →
Corner Transistor Suppression
Application:
13/112,317 →
Publication:
US 2012/0292735
Integrated Circuit Including a Stressed Dielectric Layer with Stable Stress
Application:
13/225,483 →
Publication:
US 2011/0316085
Method for Fabricating Semiconductor Devices Using Stress Engineering
Integration of Trench Mos with Low Voltage Integrated Circuits
Apparatus and Methods for Cleaning and Drying of Wafers
Application:
13/443,891 →
Publication:
US 2012/0255586
Non-Volatile Memory Using Pyramidal Nanocrystals as Electron Storage Elements
Vacuum Pump Controller
Semiconductor Device with Reduced Contact Resistance and Method of Manufacturing Thereof
Corner Transistor Suppression
Wafer Processing
Wafer Processing
Reliable Passivation Layers for Semiconductor Devices
Integration of Trench Mos with Low Voltage Integrated Circuits
Semiconductor Device and Methods for Forming a Semiconductor Device
Finfet with Isolation
Integrated Circuits Having Crack-Stop Structures and Methods for Fabricating the Same
Integrated Circuits with a Buried N Layer and Methods for Producing Such Integrated Circuits
Through via Contacts with Insulated Substrate
Reliable Interconnects
Integrated Circuits with Improved Gap Fill Dielectric and Methods for Fabricating Same
1T Sram/Dram
Isolation for Embedded Devices
Methods for Extreme Ultraviolet Mask Defect Mitigation by Multi-Patterning
Integrated Circuits with Inactive Gates and Methods of Manufacturing the Same
Integration of Memory Devices with Different Voltages
Patent:
9,406,687 →
Application:
14/664,940 →
Stitched Devices
Integrated Circuits with Overlay Marks and Methods of Manufacturing the Same
High Voltage Transistor with Reduced Isolation Breakdown
Isolation Scheme for High Voltage Device
Etch Bias Control
Methods for Fabricating Semiconductor or Micromachined Devices with Metal Structures and Methods for Forming Self-Aligned Deep Cavity Metal Structures
Patent:
9,620,373 →
Application:
14/985,800 →
Methods for Extreme Ultraviolet Mask Defect Mitigation by Multi-Patterning
Reliable Passivation Layers for Semiconductor Devices
Application:
15/055,649 →
Publication:
US 2016/0181197
Integrated Circuits with Non-Volatile Memory and Methods of Producing the Same
Patent:
9,679,905 →
Application:
15/094,555 →
Corner Transistor Suppression
Stitched Devices
Related Assignments
(6)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Sep 3, 2015
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: GLOBALFOUNDRIES U.S. 2 LLC
Reel/Frame 036550/0001 →
Assignment of Assignor's Interest
Oct 5, 2015
From: GLOBALFOUNDRIES U.S. 2 LLC; GLOBALFOUNDRIES U.S. INC.
To: GLOBALFOUNDRIES INC.
Reel/Frame 036779/0001 →
Change of Name
Nov 20, 2018
From: CHARTERED SEMICONDUCTOR MANUFACTURING PTE. LTD.
To: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
Reel/Frame 047614/0081 →
Assignment of Assignor's Interest
Jul 16, 2020
From: ALSEPHINA INNOVATIONS, INC.
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 053351/0839 →
Release of Security Interest
Nov 19, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
Reel/Frame 054481/0673 →
Release of Security Interest
Nov 20, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES INC.
Reel/Frame 054636/0001 →