Method for using a Cu BEOL process to fabricate an integrated circuit (IC) originally having an al design
View Patent ↗A semiconductor fabrication method or process is provided for fabricating an integrated circuit (IC) originally having an Al backend design using a Cu BEOL fabrication process. The method converts the Al backend design to a Cu backend design without redesigning the IC for Cu BEOL fabrication process, and uses the resultant Cu design to fabricate the IC using Cu BEOL fabrication process. The Al-Cu conversion first determines layer construction of the Al design, and then matches metal resistances of the Al design with metal resistances of a Cu design, matches intra-metal capacitances of the Al design with intra-metal capacitances of the Cu design, and matches inter-metal capacitance of the Al design with inter-metal capacitances of the Cu design.
1. A method of fabricating an IC comprising:
converting a first backend design having a first metal to a second backend design having a second metal, wherein converting comprises,
obtaining layer construction of the first backend design,
constructing a primitive layer construction for the second backend design based on the layer construction of the first type of backend design,
matching electrical characteristics of the first metal with electrical characteristics of the second metal,
generating a second backend design layout for the second backend design, and
verifying the second backend design layout and correcting violations;
providing a substrate;
frontend processing of the substrate; and
backend processing of the substrate based on the second backend design layout.
2. The method of claim 1 wherein:
the first backend design comprises an aluminum backend process
the first metal comprises aluminum;
the second backend design comprises a copper backend process; and
the second metal comprises copper.
3. The method of claim 1 wherein obtaining layer construction comprises one or more parameters including metal thicknesses, thicknesses of inter-layer dielectric layers (ILD), thicknesses of inter-metal dielectric layers (IMD) and dielectric constant of each dielectric material (ILD or IMD).
4. The method of claim 1 wherein matching electrical characteristics of the first and second metals comprises matching metal resistances of the first and second backend designs.
5. The method of claim 4 wherein matching metal resistances of the first and second backend designs comprises scaling second metal thicknesses.
6. The method of claim 5 wherein scaling second metal thicknesses comprises determining a second metal thickness corresponding to a first metal thickness based on comparing first metal resistivity with second metal resistivity.
7. The method of claim 5 wherein scaling second metal thicknesses comprises determining a second metal thickness corresponding to a first metal thickness based on a simulation result of a model for the second backend design.
8. The method of claim 7 wherein the simulation result is obtained from SPICE model simulation.
9. The method of claim 1 wherein matching electrical characteristics of the first and second metals comprises matching line resistance of line resistors of the first and second backend designs.
10. The method of claim 1 wherein matching electrical characteristics of the first and second metals comprises matching intra-level capacitances of the first backend design with intra-level capacitances of the second backend design.
11. The method of claim 10 wherein matching intra-level capacitances of the first backend design with intra-level capacitances of the second backend design comprises tuning an effective dielectric constant of intra-metal dielectric layers.
12. The method of claim 11 wherein tuning the effective dielectric constant of intra-metal dielectric layers comprises adjusting a thickness of a nitride layer.
13. The method of claim 11 wherein tuning the effective dielectric constant of intra-metal dielectric layers comprises inserting a nitride layer having a calculated thickness.
14. The method of claim 1 wherein matching electrical characteristics of the first and second metals comprises matching inter-level capacitances of the first backend design with inter-level capacitances of the second backend design.
15. The method of claim 14 wherein matching inter-metal capacitance of the first and second backend designs comprises tuning an effective dielectric constant of inter-metal dielectric layers.
16. The method of claim 15 wherein tuning the effective dielectric constant of the inter-metal dielectric layers comprises adjusting a thickness of a dielectric layer.
17. The method of claim 1 wherein converting the first backend design to the second backend design further comprises verifying the second backend design layout by a second process layout design rule checking tool and correcting violations if any determined by the second process layout design rule checking tool.
18. The method of claim 17 wherein verifying the second backend design comprises identifying any violations from one or more of:
a maximum metal width rule or a maximum metal density rule;
a minimum metal width rule or a minimum metal density rule; and
a metal size rule, a via size rule, a metal-metal spacing rule, a metal-via spacing rule, a minimum via/metal enclosure rule, or a minimum metal/via overlay rule.
19. The method of claim 18 , wherein correcting the violations identified by a maximum metal width rule or a maximum metal density rule comprises slotting a portion of Cu metallization involved in the violation.
20. The method of claim 18 , wherein correcting the violations identified by the maximum metal width rule or a maximum metal density rule comprises adjusting a second metal thickness determined by matching metal resistances of the first and second backend designs.
21. The method of claim 18 , wherein correcting the violations identified by the minimum metal width rule or a minimum metal density rule comprises inserting dummy second metallization.
22. The method of claim 1 wherein converting the first backend design to the second backend design further comprises optical proximity correction of the second backend design layout.
23. The method of claim 1 wherein converting the first backend design to the second backend design further comprises mask layer generation based on the second backend design layout.
24. A method of fabricating an IC using a second backend design employing a second metal, wherein the IC originally is based on a first backend design employing a first metal, the method comprising:
providing a first backend design;
obtaining layer construction of the first backend design;
matching electrical characteristics of the first metal with electrical characteristics of the second metal;
generating an intermediate second backend design layout for the second backend design;
verifying the second intermediate design layout;
correcting violations, if any, determined by verifying the intermediate second design layout;
generating final second design layout; and
fabricating the IC based on the final second design layout.
25. The method of claim 24 wherein if no violations are determined by verifying the intermediate second design layout, the intermediate second design layout serves as the final second design layout.
26. The method of claim 24 wherein:
the first backend design comprises an aluminum backend process;
the first metal comprises aluminum;
the second backend design comprises a copper backend process; and
the second metal comprises copper.
27. A method of converting a first backend design of an IC to a second backend design, the method comprises:
providing a first backend design;
obtaining layer construction of the first backend design, wherein the layer construction comprises one or more parameters including metal thicknesses, thicknesses of ILDs, thicknesses of IMDs and dielectric constants of dielectric materials of ILDs and IMDs;
matching electrical characteristics of the first metal with electrical characteristics of the second metal;
verifying the second backend design;
correcting violations, if any, determined by verifying the intermediate second design layout;
generating a second design layout; and
fabricating the IC based on the final second design layout.
28. The method of claim 27 wherein:
the first backend design comprises an aluminum backend process;
the first metal comprises aluminum;
the second backend design comprises a copper backend process; and
the second metal comprises copper.
29. A method of fabricating an IC comprising:
converting a first backend design having a first metal to a second backend design having a second metal, wherein converting comprises,
obtaining layer construction of the first backend design,
constructing a primitive layer construction for the second backend design based on the layer construction of the first type of backend design,
matching electrical characteristics of the first metal with electrical characteristics of the second metal, and
generating a second backend design layout for the second backend design;
providing a substrate;
frontend processing of the substrate; and
backend processing of the substrate based on the second backend design layout.