Composite stress spacer
View Patent ↗An example method embodiment forms spacers that create tensile stress on the substrate on both the PFET and NFET regions. We form PFET and NFET gates and form tensile spacers on the PFET and NFET gates. We implant first ions into the tensile PFET spacers to form neutralized stress PFET spacers. The neutralized stress PFET spacers relieve the tensile stress created by the tensile stress spacers on the substrate. This improves device performance.
1. A method of fabrication of a semiconductor device structure comprising the steps of:
a) providing a substrate having a PFET region and a NFET region, a PFET gate over said PFET region, and a NFET gate over said NFET region; said PFET gate having PFET gate sidewalls; said NFET gate having NFET gate sidewalls;
b) forming NFET source/drain regions adjacent to said NFET gate; then
c) forming tensile PFET spacers over the PFET gate sidewalls and tensile NFET spacers over the NFET gate sidewalls;
d) implanting first ions into the tensile PFET spacers to form neutralized PFET spacers whereby the first ions reduce a stress in the neutralized PFET spacers and reduce a stress in the PFET region; and
e) forming PFET source/drain regions adjacent to said PFET gate.
2. The method of claim 1 wherein the tensile PFET spacers and the tensile NFET spacers have a tensile stress between 8 Gdynes/cm 2 and 16 Gdynes/cm 2 .
3. The method of claim 1 wherein said first ions are Ge or Xe ions and the neutralized PFET spacers have a first ion concentration between 5E19/cm 3 and 1E20/cm 3 ; the first ions are implanted with a dose between 5E14/cm 2 and 1E15/cm 2 and at an energy between 30 kev and 35 kev.
4. The method of claim 1 wherein said first ions are implanted into said tensile PFET spacers and said PFET region; said first ions are Ge ions and the neutralized PFET spacers and the implanted PFET region have a first ion concentration between 5E19/cm 3 and 1E20/cm 3 ; the first ions are implanted with a dose between 5E14/cm 2 and 1E15/cm 2 and at an energy between 30 kev and 35 kev.
5. The method of claim 1 wherein the tensile PFET spacers have a tensile stress between 8 Gdynes/cm 2 and 16 Gdynes/cm 2 before the first ion implant and the neutralized PFET spacers have a tensile stress between about 2 Gdynes/cm 2 and 4 Gdynes/cm 2 after the first ion implant.
6. The method of claim 1 which further comprises:
forming first PFET spacers over said PFET gate sidewalls and forming first NFET spacers over said NFET gate sidewalls;
forming the NFET source/drain regions adjacent to said first NFET spacers;
removing said first PFET spacers and the first NFET spacers; and the neutralized PFET spacers have a first width and the first NFET spacers have a second width; the first width and the second width are not approximately equal.
7. The method of claim 1 which further comprises
forming first PFET spacers over said PFET gate sidewalls and forming first NFET spacers over said NFET gate sidewalls;
forming the NFET source/drain regions adjacent to said first NFET spacers; removing said first PFET spacers and the first NFET spacers; and
the neutralized PFET spacers are at least either 10% wider or 10% narrower than said first NFET spacers.
8. The method of claim 1 which further comprises:
forming first PFET spacers over said PFET gate sidewalls and forming first NFET spacers over said NFET gate sidewalls;
forming the NFET source/drain regions adjacent to said first NFET spacers;
removing said first PFET spacers and the first NFET spacers; and
the neutralized PFET spacers have a first width and the first NFET spacers have a second width; the first width and the second width are not approximately equal; the first width and said second width are between 450 to 650 angstroms.
9. The method of claim 1 which further includes a PFET channel in said substrate under said PFET gate and a NFET channel in said substrate under said NFET gate; the PFET channel is between about 80% and 120% the width of said NFET channel.
10. The method of claim 1 which further comprises:
forming first PFET spacers over said PFET gate sidewalls and forming first NFET spacers over said NFET gate sidewalls; then
forming the NFET source/drain regions adjacent to said first NFET spacers; and then removing said first PFET spacers and said first NFET spacers.
11. The method of claim 1 wherein step (e) is performed after step (d).
12. The method of claim 1 wherein step (a) is performed before step (b),
step (b) is performed before step (c),
step (c) is performed before step (d), and
step (d) is performed before step (e).
13. A method of fabrication of semiconductor device structure comprising the steps of:
a) providing a substrate having a PFET region and a NFET region, a nwell region in said PFET region, a PFET gate over said PFET region, and a NFET gate over said NFET region; said PFET gate having PFET gate sidewalls; said NFET gate having NFET gate sidewalls;
b) forming first PFET spacers over said PFET gate sidewalls and forming first NFET spacers over said NFET gate sidewalls;
c) forming NFET source/drain regions adjacent to said first NFET spacers;
d) removing said first PFET spacers and said first NFET spacers;
e) forming tensile PFET spacers over the PFET gate sidewalls and tensile NFET spacers over the NFET gate sidewalls;
(1) the tensile PFET spacers and the tensile NFET spacers have a tensile stress between 8 Gdynes/cm 2 and 16 Gdynes/cm 2 ;
f) implanting first ions into the tensile PFET spacers to form neutralized PFET spacers and into said PFET region whereby the first ions relax a stress in the neutralized PFET spacers and a stress in the PFET region;
(1) the neutralized PFET spacers have a tensile stress between about 2 Gdynes/cm 2 and 4 Gdynes/cm 2 after the first ion implant;
(2) said first ions are Ge or Xe ions; and
(g) implanting P type impurities into said PFET region to form PFET source/drain regions adjacent to said neutralized PFET spacers.
14. The method of claim 13 wherein the neutralized PFET spacers have a first ion concentration between 5E19/cm 3 and 1E20/cm 3 ; the first ions are implanted with a dose between 5E14/cm 2 and 1E15/cm 2 and at an energy between 30 kev and 35 kev.
15. The method of claim 13 wherein said first ions are Ge ions and the neutralized PFET spacers have a first ion concentration between 5E19/cm 3 and 1E20/cm 3 in the regions where the first ions were implanted; the first ions are implanted with a dose between 5E14/cm 2 and 1E15/cm 2 and at an energy between 30 kev and 35 kev.
16. The method of claim 13 wherein the neutralized PFET spacers have a first width and the first NFET spacers have a second width; the first width and the second width are not approximately equal; the first width and said second width are between 450 to 650 angstroms.
17. A method of fabrication of a semiconductor device structure comprising the steps of:
a) providing a substrate having a PFET region and a NFET region, a PFET gate over said PFET region, and a NFET gate over said NFET region; said PFET gate having PFET gate sidewalls; said NFET gate having NFET gate sidewalls;
b) forming first PFET spacers over said PFET gate sidewalls and forming first NFET spacers over said NFET gate sidewalls;
c) forming NFET source/drain regions adjacent to said first NFET spacers; then
d) removing said first PFET spacers and said first NFET spacers;
e) forming tensile PFET spacers over the PFET gate sidewalls and forming tensile NFET spacers over the NFET gate sidewalls;
f) implanting first ions into the tensile PFET spacers to form neutralized PFET spacers whereby the first ions reduce a stress in the neutralized PFET spacers and reduce a stress in the PFET region; and
g) forming PFET source/drain regions adjacent to said PFET gate.
18. The method of claim 17 wherein step (b) is
performed after step (a);
step (c) is performed after step (b); and
step (d) is performed after step (c).
19. The method of claim 17 wherein the neutralized PFET spacers have a first width and the first NFET spacers have a second width; the first width and the second width are not approximately equal.