Integrated circuit including a stressed dielectric layer with stable stress
View Patent ↗A method for fabricating an integrated circuit is provided. The method includes providing a substrate having an active region and an opening in the substrate adjacent to the active region. The opening is filled with a dielectric material so as to provide an isolation region in the substrate. A transistor is also formed in the active region and a pre-metal dielectric layer formed over the substrate and transistor. At least one of the dielectric layer in isolation region or the pre-metal dielectric layer includes a stressed O 3 TEOS oxide having a stress retaining dopant, wherein the concentration of the stress retaining dopant is sufficient to retard stress degradation of the O 3 TEOS oxide.
1. A method of fabricating an integrated circuit (IC) comprising:
providing a substrate having an active region and an opening in the substrate adjacent to the active region;
filling the opening with a first stress layer of O 3 TEOS oxide having a stress retaining dopant to form an isolation region in the substrate, the concentration of stress retaining dopant being sufficient to retard stress degradation of the first stress layer of O 3 TEOS oxide; and
forming a transistor on the substrate in the active region.
2. The method of claim 1 wherein the stress retaining dopant comprises nitrogen.
3. The method of claim 2 wherein the nitrogen comprises a concentration of about 1E6-1E15 c/s.
4. The method of claim 1 wherein the O 3 TEOS oxide is in-situ doped with nitrogen to form N doped O 3 TEOS oxide.
5. The method of claim 4 wherein N doped O 3 TEOS oxide is formed by chemical vapor deposition.
6. The method of claim 5 wherein the N doped O 3 TEOS oxide is deposited at a temperature of about 350-600° C. and pressure of about 50-600 Torr.
7. A method of fabricating an integrated circuit (IC) comprising:
providing a substrate having an active region and an opening in the substrate adjacent to the active region;
filling the opening with a first dielectric material to form an isolation region in the substrate;
forming a transistor on the substrate in the active region; and
forming a pre-metal dielectric (PMD) layer on the substrate and the transistor, the PMD layer comprises a second dielectric material,
wherein at least one of the first or second dielectric materials comprises a stressed O 3 TEOS oxide layer having a stress retaining dopant, the concentration of stress retaining dopant being sufficient to retard stress degradation of the stressed O 3 TEOS oxide layer.
8. The method of claim 7 wherein the stress retaining dopant comprises nitrogen.
9. The method of claim 7 further comprises providing a dielectric stress inducing liner layer on the substrate and transistor prior to forming the PMD layer.