CORNER TRANSISTOR SUPPRESSION
The threshold voltage of parasitic transistors formed at corners of shallow trench isolation regions is increased and mobility decreased by employing a high-K dielectric material. Embodiments include STI regions comprising a liner of a high-K dielectric material extending proximate trench corners. Embodiments also include STI regions having a recess formed in the trench, wherein the recess contains a high-K dielectric material, in the form of a layer or spacer, extending proximate trench corners.
1 . A method comprising:
forming a trench, having side surfaces and a bottom surface, in a substrate;
forming an oxide liner on the side surfaces and bottom surface of the trench; and
forming a layer of high-K dielectric material on the oxide liner.
2 . The method according to claim 1 , further comprising filling the trench with an insulating material.
3 . The method according to claim 1 , wherein the substrate comprises a semiconductor material, the method further comprising:
forming a pad oxide layer on an upper surface of the substrate; and
forming a pad nitride layer on the pad oxide layer, both prior to forming the trench in the substrate;
filling the trench with insulating material forming an overburden on the pad nitride layer subsequent to forming the layer of high-K dielectric material; and
planarizing such that an upper surface of the insulating material is substantially coplanar with an upper surface of the pad nitride layer, wherein
the layer of high-K dielectric material extends proximate corners of the trench.
4 . The method according to claim 3 , further comprising:
removing the pad oxide and pad nitride layers from the upper surface of the substrate, leaving the filled trench as a trench isolation region; and
forming transistors on the substrate separated by the trench isolation region, wherein,
the layer of high-K dielectric material increases a threshold voltage of and lowers mobility of a parasitic transistor formed at a trench corner.
5 . A method comprising:
forming a trench, having corners, side surfaces, and a bottom surface, in a substrate having an upper surface;
filling the trench with an insulating material;
removing insulating material from the trench to form a recess therein extending below the upper surface of the substrate; and
providing a high-K dielectric material in the recess.
6 . The method according to claim 5 , further comprising forming an oxide liner on the side surfaces and bottom surface of the trench.
7 . The method according to claim 6 , comprising providing the high-K dielectric material in the form of a layer proximate a trench corner.
8 . The method according to claim 6 , comprising providing the high-K dielectric material in the form of a spacer proximate a trench corner.
9 . The method according to claim 6 , wherein the substrate comprises a semiconductor material, the method further comprising:
forming a pad oxide layer on the upper surface of the substrate; and
forming a pad nitride layer on the pad oxide layer, both prior to forming the trench in the substrate;
filling the trench with insulating material forming an overburden of insulating material on the pad nitride layer; and
planarizing such that an upper surface of the insulating material is substantially coplanar with an upper surface of the pad nitride layer;
providing a high-K dielectric material in the recess by:
forming a layer of the high-K dielectric material over the pad nitride layer and filling the recess; and
removing portions of the high-K dielectric material from over the pad nitride layer leaving the high-K dielectric material in the recess with an upper surface which is substantially coplanar with the upper surface of the substrate, wherein
the high-K dielectric material in the recess extends proximate corners of the trench.
10 . The method according to claim 9 , further comprising:
removing the pad oxide and pad nitride layers from the upper surface of the substrate, leaving the filled trench as a trench isolation region; and
forming transistors on the substrate separated by the trench isolation region, wherein,
the high-K dielectric material in the recess increases a threshold voltage of and lowers mobility of a parasitic transistor formed at a trench corner.
11 . The method according to claim 10 , comprising providing the high-K dielectric material in the recess in the form of a layer.
12 . The method according to claim 10 , comprising providing the high-K dielectric material in the recess in the form of a spacer.
13 . A semiconductor device comprising a trench isolation region formed in a substrate, the trench isolation region comprising:
a trench having corners, side surfaces, and a bottom surface;
an oxide liner on the side surfaces and bottom surface of the trench;
a layer of high-K dielectric material on the oxide liner extending proximate trench corners; and
insulating material filling the trench.
14 . The semiconductor device according to claim 13 , further comprising transistors on the substrate separated by the trench isolation region, wherein
the layer of high-K dielectric material increases a threshold voltage of and lowers mobility of a parasitic transistor formed at a trench corner.
15 . A semiconductor device comprising trench isolation region formed in a substrate, the substrate having an upper surface, the trench isolation region comprising:
a trench having corners, side surfaces, and a bottom surface;
insulating material filling the trench;
a recess in the insulating material extending below the upper surface of the substrate; and
a high-K dielectric material in the recess extending proximate trench corners.
16 . The semiconductor device according to claim 15 , further comprising an oxide liner on the side surfaces and bottom surface of the trench.
17 . The semiconductor device according to claim 16 , further comprising transistors on the substrate separated by the trench isolation region, wherein
the high-K dielectric material in the recess increases a threshold voltage of and lowers mobility of a parasitic transistor formed at a trench corner.
18 . The semiconductor device according to claim 17 , wherein the high-K dielectric material in the recess is in the form of a layer.
19 . The semiconductor device according to claim 17 , wherein the high-K dielectric material in the recess is in the form of a spacer.
20 . A semiconductor device comprising:
transistors formed in a substrate; and
a trench isolation region formed between the transistors, the trench isolation region containing means for increasing a threshold voltage of and lowering mobility of a parasitic transistor formed at a trench corner.