Integrated circuits with non-volatile memory and methods of producing the same
View Patent ↗Integrated circuits and methods of producing the same are provide. In an exemplary embodiment, a method includes determining a memory area of the integrated circuit, and forming a select layer overlying the substrate. A portion of the select layer is selectively etched to form a select gate within the memory area. A concentration of an indicator is measured in an etch off-gas during the selective etching of the select layer, and the selective etching of the select layer is terminated when the concentration of the indicator crosses an end point determination concentration.
1. A method of producing an integrated circuit comprising:
determining a memory area of the integrated circuit;
forming a select layer overlying a substrate;
selectively etching a portion of the select layer to form a select gate, wherein the select gate is within the memory area;
measuring a concentration of an indicator in an etch off-gas during the selective etching of the select layer; and
terminating the selective etching of the select layer when a change in the concentration of the indicator crosses an end point determination concentration.
2. The method of claim 1 further comprising forming a non-volatile memory cell in the memory area, wherein the non-volatile memory cell comprises the select gate.
3. The method of claim 1 wherein measuring the concentration of the indicator comprises measuring a concentration of oxygen in the etch off-gas.
4. The method of claim 3 wherein terminating the selective etching of the select layer comprises determining when the concentration of oxygen in the etch off-gas falls below the end point determination concentration.
5. The method of claim 1 wherein:
measuring the concentration of the indicator comprises measuring a concentration of oxygen in the etch off-gas, wherein the concentration of oxygen in the etch off-gas increases from below the end point determination concentration to above the end point determination concentration during the selective etching; and
terminating selective etching of the select layer comprises terminating selective etching of the select layer when the concentration of oxygen in the etch off-gas falls below the end point determination concentration after the concentration of oxygen in the etch off-gas increased from below the end point determination concentration to above the end point determination concentration.
6. The method of claim 1 wherein etching the select layer comprises removing the select layer from a dummy area of the integrated circuit, wherein the dummy area is different than the memory area of the integrated circuit.
7. The method of claim 6 wherein etching the select layer comprises removing the select layer from at least about 20 percent of a substrate area.
8. The method of claim 6 further comprising forming a dummy gate overlying the substrate in the dummy area.
9. The method of claim 8 wherein forming the dummy gate comprises forming the dummy gate after forming the select gate.
10. The method of claim 8 further comprising:
forming a memory layer overlying the substrate prior to forming the dummy gate such that the dummy gate overlies the memory layer.
11. The method of claim 1 wherein determining the memory area comprises determining the memory area that is less than about 20 percent of a substrate area.
12. The method of claim 1 wherein etching the select layer to form the select gate further comprises removing a gate dielectric layer after etching the select layer.
13. The method of claim 1 further comprising:
forming a memory layer overlying select gate; and
forming a control gate wherein the memory layer is between the select gate and the control gate.
14. A method of producing an integrated circuit comprising:
determining a memory area and a dummy area of the integrated circuit;
forming a select layer overlying a substrate, wherein the select layer overlies the memory area and the select layer overlies the dummy area;
removing a portion of the select layer to form a select gate in the memory area with a selective etch, wherein the select layer is simultaneously removed from at least a portion of the dummy area;
measuring a concentration of an indicator in an etch off-gas during the selective etch;
terminating the selective etch when a change in the concentration of the indicator crosses an end point determination concentration; and
forming a non-volatile memory cell wherein the non-volatile memory cell comprises the select gate.
15. The method of claim 14 wherein removing the portion of the select layer comprises removing the select layer from at least about 20 percent of a substrate area.
16. The method of claim 15 wherein determining the memory area comprises determining the memory area wherein the memory area is less than about 20 percent of the substrate area.
17. The method of claim 14 further comprising:
forming a memory layer overlying the substrate; and
forming a dummy gate within the dummy area, wherein the dummy gate overlies the memory layer.
18. The method of claim 17 wherein forming the memory layer comprises forming nanocrystals within the memory layer.
19. The method of claim 17 further comprising forming a control gate simultaneously with the dummy gate, wherein the non-volatile memory cell comprises the control gate.