Semiconductor device with reduced contact resistance and method of manufacturing thereof
View Patent ↗A method (and semiconductor device) of fabricating a semiconductor device provides a filed effect transistor (FET) with reduced contact resistance (and series resistance) for improved device performance. An impurity is implanted in the source/drain (S/D) regions after contact silicide formation and a spike anneal process is performed that lowers the schottky barrier height (SBH) of the interface between the silicide and the lower junction region of the S/D regions. This results in lower contact resistance and reduces the thickness (and Rs) of the region at the silicide-semiconductor interface.
1. A method of forming a semiconductor device, the method comprising:
providing a semiconductor substrate with dopants of a first conductivity type;
forming a field-effect transistor (FET) structure on the substrate, the FET structure including a gate structure and first and second source/drain (S/D) regions with dopants of a second conductivity type;
depositing metal on the first and second S/D regions;
performing a thermal annealing process to form metal silicide within the first and second S/D regions;
after metal silicide is formed, implanting an impurity in the first and second S/D regions; and
after impurity implantation, performing a spike annealing process comprising ramping up temperature to an intended temperature in less than about 5 seconds.
2. The method in accordance with claim 1 wherein the impurity comprises nitrogen.
3. The method in accordance with claim 1 wherein the metal comprises nickel.
4. The method in accordance with claim 1 wherein the spike annealing process is a laser spike annealing (LSA) process.
5. The method in accordance with claim 4 further comprising:
after impurity implantation and prior to the spike annealing process, performing a second thermal annealing process.
6. The method in accordance with claim 5 wherein the impurity comprises nitrogen and the metal comprises nickel.
7. The method in accordance with claim 4 further comprising:
removing excess unreacted deposited metal; and
after removing excess unreacted metal and prior to impurity implantation, performing a second thermal annealing process.
8. The method in accordance with claim 7 wherein the impurity comprises nitrogen and the metal comprises nickel.
9. A method of forming a semiconductor device, the method comprising:
providing a semiconductor substrate with dopants of a first conductivity type;
forming a field-effect transistor (FET) structure on the substrate, the FET structure including a gate structure and first and second source/drain (S/D) regions with dopants of a second conductivity type;
depositing metal on the first and second S/D regions;
performing a thermal annealing process to form metal silicide within the first and second S/D regions;
prior to depositing the metal, implanting an impurity in the first and second S/D regions; and
after performing the thermal annealing process, performing a spike annealing process comprising ramping up temperature to an intended temperature in less than about 5 seconds.
10. The method in accordance with claim 9 further comprising:
prior to spike annealing, performing a second thermal annealing process.
11. A method of forming a field-effect transistor (FET) structure having reduced contact resistance, the method comprising:
forming a gate structure on a semiconductor substrate having dopants of a first conductivity type, the gate structure including a gate dielectric and a gate;
forming a first source/drain (S/D) region having dopants of a second conductivity type and positioned proximate the gate structure;
forming a second S/D region having dopants of the second conductivity type and positioned proximate the gate structure;
forming metal on the first and second S/D regions;
performing a thermal annealing process to form metal silicide within contact regions in the first and second S/D regions;
removing unreacted metal;
after removing unreacted metal, implanting an impurity in the first and second S/D regions; and
after impurity implantation, performing a spike annealing process comprising ramping up temperature to an intended temperature in less than about 5 seconds.
12. The method in accordance with claim 11 wherein the impurity comprises nitrogen.
13. The method in accordance with claim 11 wherein the metal comprises nickel.
14. The method in accordance with claim 11 wherein the spike annealing process is a laser spike annealing (LSA) process.
15. The method in accordance with claim 11 wherein the S/D regions include a contact region including metal silicide disposed therein, a segregation region and a junction region, and the impurity disposed in the first and second S/D regions is higher in concentration in the segregation region than in the contact region and the junction region.